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Mon, 24 Jun 2019 15:09:22 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::d3:794c:1b94:cf3]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::d3:794c:1b94:cf3%4]) with mapi id 15.20.2008.014; Mon, 24 Jun 2019 15:09:22 +0000 From: Robert Richter To: Borislav Petkov , James Morse , "Mauro Carvalho Chehab" CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Richter Subject: [PATCH v2 13/24] EDAC, ghes: Add support for legacy API counters Thread-Topic: [PATCH v2 13/24] EDAC, ghes: Add support for legacy API counters Thread-Index: AQHVKp7NCU80sqh790Onv0iU1Olm1Q== Date: Mon, 24 Jun 2019 15:09:22 +0000 Message-ID: <20190624150758.6695-14-rrichter@marvell.com> References: <20190624150758.6695-1-rrichter@marvell.com> In-Reply-To: <20190624150758.6695-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1P190CA0035.EURP190.PROD.OUTLOOK.COM (2603:10a6:7:52::24) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:16c::25) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [92.254.182.202] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: bbf0ae92-7722-4e57-ab32-08d6f8b5eff6 x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 4IpL94XpVy4zbOSbo1UveI0rsSP8Mbi090fbyIcNW4xPi1wOwwdlTmF+E33+cX3z3uHuAGoWkniRFBAaV+zrh0Iw6OY5R4TpvGnF7R2T0wv5vjW1SdRhbcpHq82zlmJGc2RsTSx5Ci8Y6bWwHIllatEv2mXzug5xdGdLliZzFnfIIRF38+DAibJTXtYC3mP6oHgoXxju3TeEHwwdC8uEkPjLmQFtNgxdVRSssiAZ+B646g1tqCEn6bv92JOup0tM+IRGibjosmSBVcZ02KhWWB0CR2G4cJqyaMIbqICkcFSDhweXgB7i6Ft1eG2EtxhFE42KXnTmRxT/7Rs/jDhvUQ6BuxAdcMyjxadWvHxElSoxawC3fzT0AMdVE0ld4eV6S9TXwFNa+ldFso7OHYOeQkoeMXxMmpHV4Giiw0sbW0k= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: bbf0ae92-7722-4e57-ab32-08d6f8b5eff6 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Jun 2019 15:09:22.0931 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rrichter@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3197 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-24_10:, , signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ghes driver is not able yet to count legacy API counters in sysfs, e.g.: /sys/devices/system/edac/mc/mc0/csrow2/ce_count /sys/devices/system/edac/mc/mc0/csrow2/ch0_ce_count /sys/devices/system/edac/mc/mc0/csrow2/ch1_ce_count Make counting csrows/channels generic so that the ghes driver can use it too. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 38 +++++++++++++++++++++----------------- drivers/edac/edac_mc.h | 7 ++++++- drivers/edac/ghes_edac.c | 2 +- 3 files changed, 28 insertions(+), 19 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index a8d4471e238c..eea09c6acd3e 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -1007,7 +1007,8 @@ static void edac_ue_error(struct mem_ctl_info *mci, void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, struct mem_ctl_info *mci, struct dimm_info *dimm, - struct edac_raw_error_desc *e) + struct edac_raw_error_desc *e, + int row, int chan) { char detail[80]; u8 grain_bits; @@ -1046,7 +1047,22 @@ void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, e->label, detail, e->other_detail); } + /* old API's counters */ + if (dimm) { + row = dimm->csrow; + chan = dimm->cschannel; + } + if (mci->csrows && row >= 0) { + if (type == HW_EVENT_ERR_CORRECTED) { + mci->csrows[row]->ce_count += e->error_count; + if (chan >= 0) + mci->csrows[row]->channels[chan]->ce_count += e->error_count; + } else { + mci->csrows[row]->ue_count += e->error_count; + } + edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); + } } EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error); @@ -1177,22 +1193,10 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, } } - if (!per_layer_report) { + if (!per_layer_report) strcpy(e->label, "any memory"); - } else { - edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); - if (p == e->label) - strcpy(e->label, "unknown memory"); - if (type == HW_EVENT_ERR_CORRECTED) { - if (row >= 0) { - mci->csrows[row]->ce_count += error_count; - if (chan >= 0) - mci->csrows[row]->channels[chan]->ce_count += error_count; - } - } else - if (row >= 0) - mci->csrows[row]->ue_count += error_count; - } + else if (!*e->label) + strcpy(e->label, "unknown memory"); /* Fill the RAM location data */ p = e->location; @@ -1210,6 +1214,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, dimm = edac_get_dimm(mci, top_layer, mid_layer, low_layer); - edac_raw_mc_handle_error(type, mci, dimm, e); + edac_raw_mc_handle_error(type, mci, dimm, e, row, chan); } EXPORT_SYMBOL_GPL(edac_mc_handle_error); diff --git a/drivers/edac/edac_mc.h b/drivers/edac/edac_mc.h index b816cf3caaee..c4ddd5c1e24c 100644 --- a/drivers/edac/edac_mc.h +++ b/drivers/edac/edac_mc.h @@ -216,6 +216,10 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, * @mci: a struct mem_ctl_info pointer * @dimm: a struct dimm_info pointer * @e: error description + * @row: csrow hint if there is no dimm info (<0 if + * unknown) + * @chan: cschannel hint if there is no dimm info (<0 if + * unknown) * * This raw function is used internally by edac_mc_handle_error(). It should * only be called directly when the hardware error come directly from BIOS, @@ -224,7 +228,8 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, struct mem_ctl_info *mci, struct dimm_info *dimm, - struct edac_raw_error_desc *e); + struct edac_raw_error_desc *e, + int row, int chan); /** * edac_mc_handle_error() - Reports a memory event to userspace. diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 746083876b5f..8063996a311d 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -434,7 +434,7 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) dimm_info = edac_get_dimm_by_index(mci, e->top_layer); - edac_raw_mc_handle_error(type, mci, dimm_info, e); + edac_raw_mc_handle_error(type, mci, dimm_info, e, -1, -1); spin_unlock_irqrestore(&ghes_lock, flags); }