| Message ID | 20190625164733.11091-14-jorge.ramirez-ortiz@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Support CPU frequency scaling on QCS404 | expand |
I actually think that it makes sense to squash this patch with the [PATCH v3 10/14] arm64: dts: qcom: qcs404: Add OPP table patch. But that might be a personal preference. Either way, I think this series in ready for the real mailing list. On Tue, 25 Jun 2019 at 18:48, Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> wrote: > > Support dynamic voltage and frequency scaling on qcs404. > > Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> > Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> > --- > arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi > index 9569686dbc41..4b4ce0b5df76 100644 > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi > @@ -34,6 +34,9 @@ > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > next-level-cache = <&L2_0>; > + clocks = <&apcs_glb>; > + operating-points-v2 = <&cpu_opp_table>; > + cpu-supply = <&pms405_s3>; > }; > > CPU1: cpu@101 { > @@ -43,6 +46,9 @@ > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > next-level-cache = <&L2_0>; > + clocks = <&apcs_glb>; > + operating-points-v2 = <&cpu_opp_table>; > + cpu-supply = <&pms405_s3>; > }; > > CPU2: cpu@102 { > @@ -52,6 +58,9 @@ > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > next-level-cache = <&L2_0>; > + clocks = <&apcs_glb>; > + operating-points-v2 = <&cpu_opp_table>; > + cpu-supply = <&pms405_s3>; > }; > > CPU3: cpu@103 { > @@ -61,6 +70,9 @@ > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > next-level-cache = <&L2_0>; > + clocks = <&apcs_glb>; > + operating-points-v2 = <&cpu_opp_table>; > + cpu-supply = <&pms405_s3>; > }; > > L2_0: l2-cache { > -- > 2.21.0 >
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 9569686dbc41..4b4ce0b5df76 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -34,6 +34,9 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; CPU1: cpu@101 { @@ -43,6 +46,9 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; CPU2: cpu@102 { @@ -52,6 +58,9 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; CPU3: cpu@103 { @@ -61,6 +70,9 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; L2_0: l2-cache {