From patchwork Tue Jul 9 10:29:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 168739 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp8365842ilk; Tue, 9 Jul 2019 03:29:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqy7LSejNh4fY7Ser0WbRb/X8D5AAV4g84qdS16QsBRjnwoWLIu+E7ux9rX0aFxPk+XrTRz4 X-Received: by 2002:a63:2ad5:: with SMTP id q204mr29898775pgq.140.1562668176926; Tue, 09 Jul 2019 03:29:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562668176; cv=none; d=google.com; s=arc-20160816; b=z+40Z6PF+82pvQT1bPEVuJFpQfUZniEOqp+KGd48O5t4JdsvmdWOtUPopfugvHtUOb Y6RYB/sZa390fYNXQxnDPWKlKvM8FlZbE0C/ezZ7gFA8mBSm3SDMjws3XXKQgOb2L+PO i0FhH3BCFc5Fs6YtVNnk6pxXqD2lz2Vs3dnp1J6PuLBdrvp42pdneOws86tRfwwq/lxB FTCVYRdGJaZyCKIbt+2HnG/IQwFziBWyhE/4IS8QF930RMacYiLoGnvp8vc/J37svXys xuZaa+zkmqHqNFNTZpvm/jTQRMoWuHBMUoCXim0lT2IxHBJDxHw5VYC/C6r9odSrPYlU 9neQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=eJoRKAWaNjrnJyV7l4RBDmytOestWYS0tAiRTcdjA7U=; b=axhPdQdRQAMs3+P/3ONacC5t/pVebewSbjFs6OHaF8QhQjRX3pr8bPbP8w3bkolnTV jl+CO+pAbeE0luDTt6AFX0+r7z3uANp9LkBg7+Wzi+dVsPCN3RZ+fXTaAHvKxUICgM2v Izz+DGOthyZtufHMLPo1LTWitaFHCz36L6keVbFJUKHyjUo2LJ9nqJYZvTlBgT23v+xl slUtwfGMcfKw8UF5aizeJ9J85ELt1YjrSBsblxJS2+Omab8UhJ4jzSFiroMz5IisUC8o bWfQXvlcvm/whmhpFrUpSxJsuf/PTd2J5ugctMtFpauifDITlOAfsx1f2hnKhJNGpTC8 MPJw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x185si22227740pgb.161.2019.07.09.03.29.36; Tue, 09 Jul 2019 03:29:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726309AbfGIK3g (ORCPT + 5 others); Tue, 9 Jul 2019 06:29:36 -0400 Received: from mx.socionext.com ([202.248.49.38]:38479 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726418AbfGIK3e (ORCPT ); Tue, 9 Jul 2019 06:29:34 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 09 Jul 2019 19:29:33 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 1191560629; Tue, 9 Jul 2019 19:29:33 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Tue, 9 Jul 2019 19:29:33 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id A69921A14E3; Tue, 9 Jul 2019 19:29:32 +0900 (JST) From: Kunihiko Hayashi To: Linus Walleij , Masahiro Yamada , linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH 4/5] pinctrl: uniphier: Add Pro5 PCIe pin-mux settings Date: Tue, 9 Jul 2019 19:29:15 +0900 Message-Id: <1562668156-12927-5-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1562668156-12927-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1562668156-12927-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Pro5 PCIe interface uses the following pins: XPERST, XPEWAKE, XPECLKRQ Signed-off-by: Kunihiko Hayashi --- drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index 1d418e3..577f12e 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -855,6 +855,8 @@ static const unsigned usb1_pins[] = {126, 127}; static const int usb1_muxvals[] = {0, 0}; static const unsigned usb2_pins[] = {128, 129}; static const int usb2_muxvals[] = {0, 0}; +static const unsigned pcie_pins[] = {109, 110, 111}; +static const int pcie_muxvals[] = {0, 0, 0}; static const unsigned int gpio_range_pins[] = { 89, 90, 91, 92, 93, 94, 95, 96, /* PORT0x */ 97, 98, 99, 100, 101, 102, 103, 104, /* PORT1x */ @@ -925,6 +927,7 @@ static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = { UNIPHIER_PINCTRL_GROUP(usb0), UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(pcie), UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range), }; @@ -957,6 +960,7 @@ static const char * const uart3_groups[] = {"uart3"}; static const char * const usb0_groups[] = {"usb0"}; static const char * const usb1_groups[] = {"usb1"}; static const char * const usb2_groups[] = {"usb2"}; +static const char * const pcie_groups[] = {"pcie"}; static const struct uniphier_pinmux_function uniphier_pro5_functions[] = { UNIPHIER_PINMUX_FUNCTION(emmc), @@ -979,6 +983,7 @@ static const struct uniphier_pinmux_function uniphier_pro5_functions[] = { UNIPHIER_PINMUX_FUNCTION(usb0), UNIPHIER_PINMUX_FUNCTION(usb1), UNIPHIER_PINMUX_FUNCTION(usb2), + UNIPHIER_PINMUX_FUNCTION(pcie), }; static int uniphier_pro5_get_gpio_muxval(unsigned int pin,