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[209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.30; Thu, 11 Jul 2019 22:30:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SMwR+6pd; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726096AbfGLFaa (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:30 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:44307 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFaa (ORCPT ); Fri, 12 Jul 2019 01:30:30 -0400 Received: by mail-pl1-f195.google.com with SMTP id t14so4188243plr.11 for ; Thu, 11 Jul 2019 22:30:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dkWh8S1DsW6tSZCYoLWe69ClR5UVvKugQ1/Th9fCzhU=; b=SMwR+6pdVG1+jVLkxuQVbtP/+BVTEx6rGEByEY4qdeK029SHABdRrCTMiXb+4nre45 h8O859XSPNC1NRkmJg2+4GipJ9ze5HOA/R6idJQ+Pt7C/gT7400+oVGtmwIU7nb7ULsX Oj54EVb6tOLF1SlsBurQ5iK3J3FAGqldb9vJuYmTP1R4tXxxxiXMf8TsxhbeUBNW3N0J UeWGq6ZtKrNGNghl5q2gRSIQzgEYpgWnrZ7JrGf/e5RvYg1+EE5//gzM/tZ9I+IV8fEQ OSKDS5JI3fNrLgVpfcqmN9DeAephhosWwadHtDNS6bmi0higyU99JwprNFVc7BjMjVJ9 0F+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dkWh8S1DsW6tSZCYoLWe69ClR5UVvKugQ1/Th9fCzhU=; b=k1E8Qwb6lZsNIlx7G/t96LoVxQaB6fXQZkvecmARxwsqJGJBYX8fCGkKLAQ3f/c12J euTQ2xpuGYYpmnoO8GKDu+wkvcBBddc5igPXEDLrDUtQLMaFaOGaYJcVqEQgTyzK7v1j IcvIDJLaD3yDB7pbl3GxBIfwL3/4VyTXVjkq3orb69ptKBrkN4mCLWKMpkdMO9ySHAP9 G+464sh2zShX/ruVJE1YDixjqEk8RC5r8j3b1kDCiT1pXvXF3eTb775WLvgOK0VKJMy3 BhgAWUhny0E6KHx+KdqV83PXNcEiF8FPP5Oyele9c56ocDqgBQ9+YwpsFJaXOezSwcF/ lLDw== X-Gm-Message-State: APjAAAXq7ZkzzCjIJQMiKLPcqObyN/Un5hcUnpjNkGuf0SNehkAC59Sj MblQf2IOkIkuX7d50ifHAZ4nn2lpMnM= X-Received: by 2002:a17:902:9307:: with SMTP id bc7mr8879363plb.183.1562909429452; Thu, 11 Jul 2019 22:30:29 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id 14sm6731541pgp.37.2019.07.11.22.30.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:28 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 33/43] arm64: Branch predictor hardening for Cavium ThunderX2 Date: Fri, 12 Jul 2019 10:58:21 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jayachandran C commit f3d795d9b360523beca6d13ba64c2c532f601149 upstream. Use PSCI based mitigation for speculative execution attacks targeting the branch predictor. We use the same mechanism as the one used for Cortex-A CPUs, we expect the PSCI version call to have a side effect of clearing the BTBs. Acked-by: Will Deacon Signed-off-by: Jayachandran C Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpu_errata.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index dbd7b944a37e..ff22915a2865 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -234,6 +234,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), .enable = enable_psci_bp_hardening, }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), + .enable = enable_psci_bp_hardening, + }, #endif { }