| Message ID | 20190719081326.9347-1-m.szyprowski@samsung.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Fix USB3.0 DRD PHY calibration issues (DWC3/XHCI) on Exynos542x SoCs | expand |
Hi Marek, On Fri, 19 Jul 2019 at 13:43, Marek Szyprowski <m.szyprowski@samsung.com> wrote: > > Calls to USB2 generic PHY calibrate() method has been moved to HCD core, > which now successfully handles generic PHYs and their calibration after > every HCD reset. This fixes all the timing issues related to PHY > calibration done directly from DWC3 driver: incorrect operation after > system suspend/resume or USB3.0 detection failure when XHCI-plat driver > compiled as separate module. > Tested on my XU3 / XU4 / HC1 Tested-by: Anand Moon <linux.amoon@gmail.com> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > --- > drivers/usb/dwc3/core.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > index c9bb93a2c81e..7dd6d419254d 100644 > --- a/drivers/usb/dwc3/core.c > +++ b/drivers/usb/dwc3/core.c > @@ -168,7 +168,6 @@ static void __dwc3_set_mode(struct work_struct *work) > otg_set_vbus(dwc->usb2_phy->otg, true); > phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); > phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); > - phy_calibrate(dwc->usb2_generic_phy); > } > break; > case DWC3_GCTL_PRTCAP_DEVICE: > @@ -1166,7 +1165,6 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) > dev_err(dev, "failed to initialize host\n"); > return ret; > } > - phy_calibrate(dwc->usb2_generic_phy); > break; > case USB_DR_MODE_OTG: > INIT_WORK(&dwc->drd_work, __dwc3_set_mode); > -- > 2.17.1 >
Hi Marek, Tested on my XU4 Tested-by: Jochen Sprickerhof <jochen@sprickerhof.de> * Anand Moon <linux.amoon@gmail.com> [2019-07-23 00:30]: >Hi Marek, > >On Fri, 19 Jul 2019 at 13:43, Marek Szyprowski <m.szyprowski@samsung.com> wrote: >> >> Calls to USB2 generic PHY calibrate() method has been moved to HCD core, >> which now successfully handles generic PHYs and their calibration after >> every HCD reset. This fixes all the timing issues related to PHY >> calibration done directly from DWC3 driver: incorrect operation after >> system suspend/resume or USB3.0 detection failure when XHCI-plat driver >> compiled as separate module. >> > >Tested on my XU3 / XU4 / HC1 >Tested-by: Anand Moon <linux.amoon@gmail.com> > > >> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> >> --- >> drivers/usb/dwc3/core.c | 2 -- >> 1 file changed, 2 deletions(-) >> >> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c >> index c9bb93a2c81e..7dd6d419254d 100644 >> --- a/drivers/usb/dwc3/core.c >> +++ b/drivers/usb/dwc3/core.c >> @@ -168,7 +168,6 @@ static void __dwc3_set_mode(struct work_struct *work) >> otg_set_vbus(dwc->usb2_phy->otg, true); >> phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); >> phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); >> - phy_calibrate(dwc->usb2_generic_phy); >> } >> break; >> case DWC3_GCTL_PRTCAP_DEVICE: >> @@ -1166,7 +1165,6 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) >> dev_err(dev, "failed to initialize host\n"); >> return ret; >> } >> - phy_calibrate(dwc->usb2_generic_phy); >> break; >> case USB_DR_MODE_OTG: >> INIT_WORK(&dwc->drd_work, __dwc3_set_mode); >> -- >> 2.17.1 >> >
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index c9bb93a2c81e..7dd6d419254d 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -168,7 +168,6 @@ static void __dwc3_set_mode(struct work_struct *work) otg_set_vbus(dwc->usb2_phy->otg, true); phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); - phy_calibrate(dwc->usb2_generic_phy); } break; case DWC3_GCTL_PRTCAP_DEVICE: @@ -1166,7 +1165,6 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) dev_err(dev, "failed to initialize host\n"); return ret; } - phy_calibrate(dwc->usb2_generic_phy); break; case USB_DR_MODE_OTG: INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
Calls to USB2 generic PHY calibrate() method has been moved to HCD core, which now successfully handles generic PHYs and their calibration after every HCD reset. This fixes all the timing issues related to PHY calibration done directly from DWC3 driver: incorrect operation after system suspend/resume or USB3.0 detection failure when XHCI-plat driver compiled as separate module. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> --- drivers/usb/dwc3/core.c | 2 -- 1 file changed, 2 deletions(-) -- 2.17.1