[03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn

Message ID 20190726175032.6769-4-richard.henderson@linaro.org
State New
Headers show
Series
  • target/arm: Convert aa32 base isa to decodetree
Related show

Commit Message

Richard Henderson July 26, 2019, 5:49 p.m.
The address of the current insn is still available in s->base.pc_next.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/translate.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

-- 
2.17.1

Comments

Peter Maydell July 29, 2019, 1:50 p.m. | #1
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> The address of the current insn is still available in s->base.pc_next.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/translate.c | 8 ++++----

>  1 file changed, 4 insertions(+), 4 deletions(-)

>

> diff --git a/target/arm/translate.c b/target/arm/translate.c

> index 33f78296eb..19b126d4f3 100644

> --- a/target/arm/translate.c

> +++ b/target/arm/translate.c

> @@ -1256,12 +1256,12 @@ static void gen_exception_insn(DisasContext *s, int excp, int syn,

>      s->base.is_jmp = DISAS_NORETURN;

>  }

>

> -static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)

> +static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)

>  {

>      TCGv_i32 tcg_syn;

>

>      gen_set_condexec(s);

> -    gen_set_pc_im(s, s->pc - offset);

> +    gen_set_pc_im(s, s->base.pc_next);

>      tcg_syn = tcg_const_i32(syn);

>      gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);

>      tcg_temp_free_i32(tcg_syn);

> @@ -8139,7 +8139,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

>              case 1:

>                  /* bkpt */

>                  ARCH(5);

> -                gen_exception_bkpt_insn(s, 4, syn_aa32_bkpt(imm16, false));

> +                gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false));

>                  break;

>              case 2:

>                  /* Hypervisor call (v7) */

> @@ -11611,7 +11611,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)

>          {

>              int imm8 = extract32(insn, 0, 8);

>              ARCH(5);

> -            gen_exception_bkpt_insn(s, 2, syn_aa32_bkpt(imm8, true));

> +            gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true));

>              break;

>          }


Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


thanks
-- PMM

Patch

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 33f78296eb..19b126d4f3 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1256,12 +1256,12 @@  static void gen_exception_insn(DisasContext *s, int excp, int syn,
     s->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
+static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
 {
     TCGv_i32 tcg_syn;
 
     gen_set_condexec(s);
-    gen_set_pc_im(s, s->pc - offset);
+    gen_set_pc_im(s, s->base.pc_next);
     tcg_syn = tcg_const_i32(syn);
     gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
     tcg_temp_free_i32(tcg_syn);
@@ -8139,7 +8139,7 @@  static void disas_arm_insn(DisasContext *s, unsigned int insn)
             case 1:
                 /* bkpt */
                 ARCH(5);
-                gen_exception_bkpt_insn(s, 4, syn_aa32_bkpt(imm16, false));
+                gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false));
                 break;
             case 2:
                 /* Hypervisor call (v7) */
@@ -11611,7 +11611,7 @@  static void disas_thumb_insn(DisasContext *s, uint32_t insn)
         {
             int imm8 = extract32(insn, 0, 8);
             ARCH(5);
-            gen_exception_bkpt_insn(s, 2, syn_aa32_bkpt(imm8, true));
+            gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true));
             break;
         }