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[209.132.180.67]) by mx.google.com with ESMTP id ch18si32232418plb.76.2019.08.01.01.20.00; Thu, 01 Aug 2019 01:20:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gyCpFTJu; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731026AbfHAIT7 (ORCPT + 14 others); Thu, 1 Aug 2019 04:19:59 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:47092 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730381AbfHAIT7 (ORCPT ); Thu, 1 Aug 2019 04:19:59 -0400 Received: by mail-pl1-f193.google.com with SMTP id c2so31830981plz.13 for ; Thu, 01 Aug 2019 01:19:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2QHSmiN7bxUJS4+X9m2RMygxyxd4x6cpBibWrQPbZA4=; b=gyCpFTJuLM7MvHrK8TfXUg8OQIEf7DynnCZ6YICKbZ9EiGi8EM99TONAPxKGNc6kQm 3hFuJY62i5Ew+NEtv8tSafNG/qzhe+cjGbtSARPHQUEgyKa7zHEXbRZAV4BDT2ZJm6vJ jsLinmkCLSYDBM41ms3BOPj8dWBOwQy+qV8V5vfjzLG2LWvD7CT76RgDp7eQxoUPllQP vB6D8S6tyncSIKwqOQTMSKQsjlWIlrO3dpDkeEEquvQuhJq8dk9JzFU9i1ub9dz0xX/t usBd+1LWn0IdleXWHo43HxgyU9wCR0JTA+VhNBKRy+wm9IC1f13K/7l7mVnHPaBOBMZd 3YAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2QHSmiN7bxUJS4+X9m2RMygxyxd4x6cpBibWrQPbZA4=; b=TyJTefNmzq7wcL7ESOB2NXUMj9dYtyiQdMwOu8NHHGLst2Jk7MIPDXMFE+FLNinzg7 HZGtoKxaU1N66iWDpWvpfJ6uM9X+aXnihE/6pJgoLqnxOPskLXwTUoHr6YtNI04dKqN4 Mw0o9KhUmwhA7esmpMl6wWfTfC0w5Md2tPf+kA532QjApmAfGBYIW3X8NUenysh8CZxW O9NwqSE/TJf6a/ASdxbrHEnxajz9pjsBYDz7aXzYGSE/o0Pmn+xZ283Yxqya7ZgGQY7Y akSt3sI1IPvvyS39VfY9iPKzQQxiB7HbXi8gncT+oT/sVLXoGM/MTGc+WWw85s3zAWbu SH8Q== X-Gm-Message-State: APjAAAUCQszeKYRj6LrkAdBFq4XE69vfefCftCL6iyp+JT2VlN4YcixJ lEAlO59Co/pETAbOeaZNRuVuGVlwmpA= X-Received: by 2002:a17:902:968d:: with SMTP id n13mr77405641plp.257.1564647598670; Thu, 01 Aug 2019 01:19:58 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id l1sm91580486pfl.9.2019.08.01.01.19.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:19:58 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 09/47] ARM: add more CPU part numbers for Cortex and Brahma B15 CPUs Date: Thu, 1 Aug 2019 13:45:53 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Russell King Commit f5683e76f35b4ec5891031b6a29036efe0a1ff84 upstream. Add CPU part numbers for Cortex A53, A57, A72, A73, A75 and the Broadcom Brahma B15 CPU. Signed-off-by: Russell King Acked-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/include/asm/cputype.h | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index e9d04f475929..76bb3bd060d1 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -74,8 +74,16 @@ #define ARM_CPU_PART_CORTEX_A12 0x4100c0d0 #define ARM_CPU_PART_CORTEX_A17 0x4100c0e0 #define ARM_CPU_PART_CORTEX_A15 0x4100c0f0 +#define ARM_CPU_PART_CORTEX_A53 0x4100d030 +#define ARM_CPU_PART_CORTEX_A57 0x4100d070 +#define ARM_CPU_PART_CORTEX_A72 0x4100d080 +#define ARM_CPU_PART_CORTEX_A73 0x4100d090 +#define ARM_CPU_PART_CORTEX_A75 0x4100d0a0 #define ARM_CPU_PART_MASK 0xff00fff0 +/* Broadcom cores */ +#define ARM_CPU_PART_BRAHMA_B15 0x420000f0 + #define ARM_CPU_XSCALE_ARCH_MASK 0xe000 #define ARM_CPU_XSCALE_ARCH_V1 0x2000 #define ARM_CPU_XSCALE_ARCH_V2 0x4000