From patchwork Mon Aug 12 17:30:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 171116 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3124264ily; Mon, 12 Aug 2019 10:35:42 -0700 (PDT) X-Received: by 2002:a5e:c918:: with SMTP id z24mr17000698iol.234.1565631102778; Mon, 12 Aug 2019 10:31:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqw7atj6EU0GfpSvNwCLM1SbqRnpcv3LU+i5R1cF6b/7g4QNFWtoxulJ/VyQC9LZcqKmV6dd X-Received: by 2002:a5e:c918:: with SMTP id z24mr17000635iol.234.1565631101804; Mon, 12 Aug 2019 10:31:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565631101; cv=none; d=google.com; s=arc-20160816; b=WeaQU8M1LFjEWBj2ApcLwVsGaFPijP4FtS9EWoFQDYYaTeAFK0rRoZpz1k3qTvXJMo B+NHLSG2/HNNew3AuxTjHtY9VZgQyaivKe+Auw6Nx91S7yGd3bToxyQItdaS6s4nlqN8 L3UaCkL6cR+W/s8QMZQDqalhViBZW30HntoXR9YJRWv6acE56GSORyK4YV+GfBVMWtGV scsmNTJ0ug1YLHq9U5T778N0ZS+Z0JUQIxynvfo0WbHsyRJs0rC2E5Ck1ctISAYrPDlL R3K4qdI7F0fxzR9NTWJ54k6GqpmVat8k7SheZV3A3fMOZKdNp0/YOHgTTm8sC9RhAXAZ teBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=jAjlCgDnGJiKnR0+9/uphuRtfbp8Lvc2+KF5nkGdnNA=; b=K/vb73i4LVR7Oz+ts5j/ik8XsGBAeic43D2f5zMcqjMz1ZoGnAWCqeN0wZqCVHvJSQ ZiuLITd0fgBGZXeRCIEbWtOtIwo7pSGCHI32/Aht/w8tvrw2EmIouN0BWmKf4C3znYEo +86hwXSKSaGafHe0w57i8qpXkAN2hf+epBfjGS32zVQSSJ4MRgJh8qayg09ugP5kzxi8 C/366VV3uNdRDySEMWDnbvn6EfwP1JTfJmrHb9koVAdksee0rqffTvP4NmU1uxJfRlfQ Du99JQ/9msonmtkAheS0P01QXNv90nsLgI5q9aAuo9ZdsOiJn9gKbNZg+X5WiE0zG+EW AvmA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 185si14299865jau.87.2019.08.12.10.31.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Aug 2019 10:31:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hxE9i-0006y6-JX; Mon, 12 Aug 2019 17:30:50 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hxE9h-0006vS-25 for xen-devel@lists.xenproject.org; Mon, 12 Aug 2019 17:30:49 +0000 X-Inumbo-ID: ec34de73-bd26-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id ec34de73-bd26-11e9-8980-bc764e045a96; Mon, 12 Aug 2019 17:30:48 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 07E48174E; Mon, 12 Aug 2019 10:30:48 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 566DF3F706; Mon, 12 Aug 2019 10:30:47 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 12 Aug 2019 18:30:14 +0100 Message-Id: <20190812173019.11956-24-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190812173019.11956-1-julien.grall@arm.com> References: <20190812173019.11956-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v3 23/28] xen/arm32: head: Setup HTTBR in enable_mmu() and add missing isb X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, HTTBR is setup in create_page_tables(). This is fine as it is called by every CPUs. However, such assumption may not hold in the future. To make change easier, the HTTBR is not setup in enable_mmu(). Take the opportunity to add the missing isb() to ensure the HTTBR is seen before the MMU is turned on. Lastly, the only use of r5 in create_page_tables() is now removed. So the register can be removed from the clobber list of the function. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v3: - Move the comment in the correct place - r5 is not cloberred anymore Changes in v2: - Patch added --- xen/arch/arm/arm32/head.S | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 3c18037575..2317fb8855 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -359,7 +359,7 @@ ENDPROC(cpu_init) * r9 : paddr(start) * r10: phys offset * - * Clobbers r0 - r6 + * Clobbers r0 - r4, r6 * * Register usage within this function: * r6 : Identity map in place @@ -374,11 +374,8 @@ create_page_tables: moveq r6, #1 /* r6 := identity map now in place */ movne r6, #0 /* r6 := identity map not yet in place */ - /* Write Xen's PT's paddr into the HTTBR */ ldr r4, =boot_pgtable add r4, r4, r10 /* r4 := paddr (boot_pagetable) */ - mov r5, #0 /* r4:r5 is paddr (boot_pagetable) */ - mcrr CP64(r4, r5, HTTBR) /* Setup boot_pgtable: */ ldr r1, =boot_second @@ -484,6 +481,13 @@ enable_mmu: mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLBs */ dsb nsh + /* Write Xen's PT's paddr into the HTTBR */ + ldr r0, =boot_pgtable + add r0, r0, r10 /* r0 := paddr (boot_pagetable) */ + mov r1, #0 /* r0:r1 is paddr (boot_pagetable) */ + mcrr CP64(r0, r1, HTTBR) + isb + mrc CP32(r0, HSCTLR) /* Enable MMU and D-cache */ orr r0, r0, #(SCTLR_Axx_ELx_M|SCTLR_Axx_ELx_C)