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[209.132.180.131]) by mx.google.com with ESMTPS id j2si504906pjw.1.2019.08.20.11.33.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Aug 2019 11:33:44 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-507392-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=s29FZd43; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=WpvtRaJr; spf=pass (google.com: domain of gcc-patches-return-507392-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-507392-patch=linaro.org@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=F9vKPqmOWPrrMF7Q5s69QLRjRkqaaQ82e324YAj7pSoUUK IKIgTn1ZkuCpx+nQADnbsFeGoCT+KTWTgALnD9Txg7SpUm3kECLy4UvP8io9p0Zf iA/fi0smBv7AGThbH3ZPMmDBG05+Bdl2jUD413ihpsKFZlg36eKpQsrqXiIMc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=AAHDPFwLevcXy3t0rVpnX10nMyA=; b=s29FZd436EwCMfOHAdJP um2L1wcB0X8U2VJLwXiNTM33oAlM8NydgWSjroRu9LCgG25uLE6hxjzRF7CCR95c FK++gP0ZPBZ5aWbK8YFJVBXTlFiAgMXfuJubuF/xeRxs/3A5QwBvskpQ9KMimC/G rgq/EJyjRSMWVOw8S3c9z+I= Received: (qmail 15102 invoked by alias); 20 Aug 2019 18:33:32 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 15093 invoked by uid 89); 20 Aug 2019 18:33:31 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-21.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_PASS, SUBJ_ALL_CAPS autolearn=ham version=3.3.1 spammy=20190821, 2019-08-21 X-HELO: mail-lj1-f174.google.com Received: from mail-lj1-f174.google.com (HELO mail-lj1-f174.google.com) (209.85.208.174) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 20 Aug 2019 18:33:29 +0000 Received: by mail-lj1-f174.google.com with SMTP id e27so6052939ljb.7 for ; Tue, 20 Aug 2019 11:33:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:from:date:message-id:subject:to; bh=FsUBPoGM+KtMttEVmhJuqvv91Xk4S3Vd3oeVic2tgL8=; b=WpvtRaJrIWj9lduPWbGvM0gzmJqcywknEifKedWi9BFWkwtLyMBnpb5xY6tTWRKUAX oaqsMKE8ePAeGpQa25U3XD3JZrIJPGiKyc9RRUoqlisnDhl9XhXpesoF+XLlpZATotwR 67gdFMry7quiAt/RgBSOnoSc5e8zz2F42qVoD3EEtJPRC2lv7GAj2rl6ZVDth5iL40oP M23VxStcb5Dxl6iJldr42lukMe44QzOpagYyHwx/YEzKYl4MZa90dc+npz2V8Gdc4Uy5 eKWNcZMaeh0X1mapjIt9L77XsmzodaxArUTslF36GKBwv8FGjLxHsxukxZg4qqe6wIWR y7/g== MIME-Version: 1.0 From: Prathamesh Kulkarni Date: Wed, 21 Aug 2019 00:02:49 +0530 Message-ID: Subject: [SVE] PR88839 To: gcc Patches , Richard Sandiford X-IsSubscribed: yes Hi, The attached patch is a fix for PR88839 ported from sve-acle-branch. OK to commit to trunk ? Thanks, Prathamesh 2019-08-21 Prathamesh Kulkarni Richard Sandiford PR target/88839 * config/aarch64/aarch64.c (aarch64_evpc_sel): New function. (aarch64_expand_vec_perm_const_1): Call aarch64_evpc_sel. testsuite/ * gcc.target/aarch64/sve/sel_1.c: New test. * gcc.target/aarch64/sve/sel_2.c: Likewise. * gcc.target/aarch64/sve/sel_3.c: Likewise. * gcc.target/aarch64/sve/sel_4.c: Likewise. * gcc.target/aarch64/sve/sel_5.c: Likewise. * gcc.target/aarch64/sve/sel_6.c: Likewise. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ec60e972f5f..f8d5270b982 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -16632,6 +16632,50 @@ aarch64_evpc_sve_tbl (struct expand_vec_perm_d *d) return true; } +/* Try to implement D using SVE SEL instruction. */ + +static bool +aarch64_evpc_sel (struct expand_vec_perm_d *d) +{ + machine_mode vmode = d->vmode; + int nunits = GET_MODE_UNIT_SIZE (vmode); + + if (d->vec_flags != VEC_SVE_DATA + || nunits > 8) + return false; + + int n_patterns = d->perm.encoding ().npatterns (); + poly_int64 vec_len = d->perm.length (); + + for (int i = 0; i < n_patterns; ++i) + if (!known_eq (d->perm[i], i) + && !known_eq (d->perm[i], vec_len + i)) + return false; + + for (int i = n_patterns; i < n_patterns * 2; i++) + if (!d->perm.series_p (i, n_patterns, i, n_patterns) + && !d->perm.series_p (i, n_patterns, vec_len + i, n_patterns)) + return false; + + if (d->testing_p) + return true; + + machine_mode pred_mode = aarch64_sve_pred_mode (nunits).require (); + + rtx_vector_builder builder (pred_mode, n_patterns, 2); + for (int i = 0; i < n_patterns * 2; i++) + { + rtx elem = known_eq (d->perm[i], i) ? CONST1_RTX (BImode) + : CONST0_RTX (BImode); + builder.quick_push (elem); + } + + rtx const_vec = builder.build (); + rtx pred = force_reg (pred_mode, const_vec); + emit_insn (gen_vcond_mask (vmode, vmode, d->target, d->op1, d->op0, pred)); + return true; +} + static bool aarch64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) { @@ -16664,6 +16708,8 @@ aarch64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) return true; else if (aarch64_evpc_trn (d)) return true; + else if (aarch64_evpc_sel (d)) + return true; if (d->vec_flags == VEC_SVE_DATA) return aarch64_evpc_sve_tbl (d); else if (d->vec_flags == VEC_ADVSIMD) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/sel_1.c b/gcc/testsuite/gcc.target/aarch64/sve/sel_1.c new file mode 100644 index 00000000000..e651e5b93b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/sel_1.c @@ -0,0 +1,27 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O2 -msve-vector-bits=256 --save-temps" } */ + +#include + +typedef int8_t vnx16qi __attribute__((vector_size (32))); + +/* Predicate vector: 1 0 1 0 ... */ + +#define MASK_32 { 0, 33, 2, 35, 4, 37, 6, 39, 8, 41, \ + 10, 43, 12, 45, 14, 47, 16, 49, 18, 51, \ + 20, 53, 22, 55, 24, 57, 26, 59, 28, 61, 30, 63 } + +#define INDEX_32 vnx16qi + +#define PERMUTE(type, nunits) \ +type permute_##type (type x, type y) \ +{ \ + return __builtin_shuffle (x, y, (INDEX_##nunits) MASK_##nunits); \ +} + +PERMUTE(vnx16qi, 32) + +/* { dg-final { scan-assembler-not {\ttbl\t} } } */ + +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.b, p[0-9]+, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.h, vl16\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/sel_2.c b/gcc/testsuite/gcc.target/aarch64/sve/sel_2.c new file mode 100644 index 00000000000..05391474a92 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/sel_2.c @@ -0,0 +1,41 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O2 -msve-vector-bits=256 --save-temps" } */ + +#include + +typedef int8_t vnx16qi __attribute__((vector_size (32))); +typedef int16_t vnx8hi __attribute__((vector_size (32))); +typedef int32_t vnx4si __attribute__((vector_size (32))); + +typedef _Float16 vnx8hf __attribute__((vector_size (32))); +typedef float vnx4sf __attribute__((vector_size (32))); + +/* Predicate vector: 1 0 0 0 ... */ + +#define MASK_32 { 0, 33, 34, 35, 4, 37, 38, 39, 8, 41, 42, 43, 12, \ + 45, 46, 47, 16, 49, 50, 51, 20, 53, 54, 55, 24, \ + 57, 58, 59, 28, 61, 62, 63 } + +/* Predicate vector: 1 0 1 0 ... */ + +#define MASK_16 {0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31} + +#define INDEX_32 vnx16qi +#define INDEX_16 vnx8hi + +#define PERMUTE(type, nunits) \ +type permute_##type (type x, type y) \ +{ \ + return __builtin_shuffle (x, y, (INDEX_##nunits) MASK_##nunits); \ +} + +PERMUTE(vnx16qi, 32) +PERMUTE(vnx8hi, 16) +PERMUTE(vnx8hf, 16) + +/* { dg-final { scan-assembler-not {\ttbl\t} } } */ + +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.b, p[0-9]+, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-9]+, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s, vl8\n} 3 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/sel_3.c b/gcc/testsuite/gcc.target/aarch64/sve/sel_3.c new file mode 100644 index 00000000000..a87492d9df1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/sel_3.c @@ -0,0 +1,50 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O2 -msve-vector-bits=256 --save-temps" } */ + +#include + +typedef int8_t vnx16qi __attribute__((vector_size (32))); +typedef int16_t vnx8hi __attribute__((vector_size (32))); +typedef int32_t vnx4si __attribute__((vector_size (32))); +typedef _Float16 vnx8hf __attribute__((vector_size (32))); +typedef float vnx4sf __attribute__((vector_size (32))); + +/* Predicate vector: 1 0 0 0 0 0 0 0 ... */ + +#define MASK_32 { 0, 33, 34, 35, 36, 37, 38, 39, \ + 8, 41, 42, 43, 44, 45, 46, 47, \ + 16, 49, 50, 51, 52, 53, 54, 55, \ + 24, 57, 58, 59, 60, 61, 62, 63 } + +/* Predicate vector: 1 0 0 0 ... */ + +#define MASK_16 { 0, 17, 18, 19, 4, 21, 22, 23, \ + 8, 25, 26, 27, 12, 29, 30, 31 } + +/* Predicate vector: 1 0 ... */ + +#define MASK_8 { 0, 9, 2, 11, 4, 13, 6, 15 } + +#define INDEX_32 vnx16qi +#define INDEX_16 vnx8hi +#define INDEX_8 vnx4si + +#define PERMUTE(type, nunits) \ +type permute_##type (type x, type y) \ +{ \ + return __builtin_shuffle (x, y, (INDEX_##nunits) MASK_##nunits); \ +} + +PERMUTE(vnx16qi, 32) +PERMUTE(vnx8hi, 16) +PERMUTE(vnx4si, 8) +PERMUTE(vnx8hf, 16) +PERMUTE(vnx4sf, 8) + +/* { dg-final { scan-assembler-not {\ttbl\t} } } */ + +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.b, p[0-9]+, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-9]+, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-9]+, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d, vl4\n} 5 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/sel_4.c b/gcc/testsuite/gcc.target/aarch64/sve/sel_4.c new file mode 100644 index 00000000000..e9bbc5527d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/sel_4.c @@ -0,0 +1,50 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O2 -msve-vector-bits=256 --save-temps" } */ + +#include + +typedef int8_t vnx16qi __attribute__((vector_size (32))); +typedef int16_t vnx8hi __attribute__((vector_size (32))); +typedef int32_t vnx4si __attribute__((vector_size (32))); +typedef int64_t vnx2di __attribute__((vector_size (32))); + +typedef _Float16 vnx8hf __attribute__((vector_size (32))); +typedef float vnx4sf __attribute__((vector_size (32))); +typedef double vnx2df __attribute__((vector_size (32))); + +/* Predicate vector: 1 1 0 0 ... */ + +#define MASK_32 { 0, 1, 34, 35, 4, 5, 38, 39, 8, 9, 42, 43, 12, 13, \ + 46, 47, 16, 17, 50, 51, 20, 21, 54, 55, 24, 25, \ + 58, 59, 28, 29, 62, 63 } + +#define MASK_16 {0, 1, 18, 19, 4, 5, 22, 23, 8, 9, 26, 27, 12, 13, 30, 31} +#define MASK_8 {0, 1, 10, 11, 4, 5, 14, 15} +#define MASK_4 {0, 1, 6, 7} + +#define INDEX_32 vnx16qi +#define INDEX_16 vnx8hi +#define INDEX_8 vnx4si +#define INDEX_4 vnx2di + +#define PERMUTE(type, nunits) \ +type permute_##type (type x, type y) \ +{ \ + return __builtin_shuffle (x, y, (INDEX_##nunits) MASK_##nunits); \ +} + +PERMUTE(vnx16qi, 32) +PERMUTE(vnx8hi, 16) +PERMUTE(vnx4si, 8) +PERMUTE(vnx2di, 4) + +PERMUTE(vnx8hf, 16) +PERMUTE(vnx4sf, 8) +PERMUTE(vnx2df, 4) + +/* { dg-final { scan-assembler-not {\ttbl\t} } } */ + +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.b, p[0-9]+, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-9]+, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-9]+, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-9]+, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/sel_5.c b/gcc/testsuite/gcc.target/aarch64/sve/sel_5.c new file mode 100644 index 00000000000..935abb54dd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/sel_5.c @@ -0,0 +1,50 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O2 -msve-vector-bits=256 --save-temps" } */ + +#include + +typedef int8_t vnx16qi __attribute__((vector_size (32))); +typedef int16_t vnx8hi __attribute__((vector_size (32))); +typedef int32_t vnx4si __attribute__((vector_size (32))); +typedef int64_t vnx2di __attribute__((vector_size (32))); + +typedef _Float16 vnx8hf __attribute__((vector_size (32))); +typedef float vnx4sf __attribute__((vector_size (32))); +typedef double vnx2df __attribute__((vector_size (32))); + +/* Predicate vector: 1 0 0 1 ... */ + +#define MASK_32 { 0, 33, 34, 3, 4, 37, 38, 7, 8, 41, 42, 11, 12, 45, 46, \ + 15, 16, 49, 50, 19, 20, 53, 54, 23, 24, 57, 58, 27, 28, \ + 61, 62, 31 } + +#define MASK_16 {0, 17, 18, 3, 4, 21, 22, 7, 8, 25, 26, 11, 12, 29, 30, 15} +#define MASK_8 {0, 9, 10, 3, 4, 13, 14, 7} +#define MASK_4 {0, 5, 6, 3} + +#define INDEX_32 vnx16qi +#define INDEX_16 vnx8hi +#define INDEX_8 vnx4si +#define INDEX_4 vnx2di + +#define PERMUTE(type, nunits) \ +type permute_##type (type x, type y) \ +{ \ + return __builtin_shuffle (x, y, (INDEX_##nunits) MASK_##nunits); \ +} + +PERMUTE(vnx16qi, 32) +PERMUTE(vnx8hi, 16) +PERMUTE(vnx4si, 8) +PERMUTE(vnx2di, 4) + +PERMUTE(vnx8hf, 16) +PERMUTE(vnx4sf, 8) +PERMUTE(vnx2df, 4) + +/* { dg-final { scan-assembler-not {\ttbl\t} } } */ + +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.b, p[0-9]+, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-9]+, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-9]+, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-9]+, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/sel_6.c b/gcc/testsuite/gcc.target/aarch64/sve/sel_6.c new file mode 100644 index 00000000000..772938f68a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/sel_6.c @@ -0,0 +1,42 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O2 -msve-vector-bits=256 --save-temps" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size (32))); +typedef int64_t vnx2di __attribute__((vector_size (32))); + +typedef float vnx4sf __attribute__((vector_size (32))); +typedef double vnx2df __attribute__((vector_size (32))); + +/* Predicate vector: 1 0 0 0 ... */ + +#define MASK_32 { 0, 33, 34, 35, 4, 37, 38, 39, 8, 41, 42, 43, 12, \ + 45, 46, 47, 16, 49, 50, 51, 20, 53, 54, 55, 24, \ + 57, 58, 59, 28, 61, 62, 63 } + +#define MASK_16 {0, 17, 18, 19, 4, 21, 22, 23, 8, 25, 26, 27, 12, 29, 30, 31} +#define MASK_8 {0, 9, 10, 11, 4, 13, 14, 15} +#define MASK_4 {0, 5, 6, 7} + +#define INDEX_8 vnx4si +#define INDEX_4 vnx2di + +#define PERMUTE(type, nunits) \ +type permute_##type (type x, type y) \ +{ \ + return __builtin_shuffle (x, y, (INDEX_##nunits) MASK_##nunits); \ +} + +PERMUTE(vnx4si, 8) +PERMUTE(vnx2di, 4) + +PERMUTE(vnx4sf, 8) +PERMUTE(vnx2df, 4) + +/* { dg-final { scan-assembler-not {\ttbl\t} } } */ + +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-9]+, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-9]+, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d, vl4\n} 2 } } */