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[209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.14; Thu, 29 Aug 2019 04:36:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mcZvlnlT; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727122AbfH2LgN (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:13 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:34944 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727066AbfH2LgN (ORCPT ); Thu, 29 Aug 2019 07:36:13 -0400 Received: by mail-pl1-f194.google.com with SMTP id gn20so1458889plb.2 for ; Thu, 29 Aug 2019 04:36:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sqSfnQDS8sjUZN/3AxA8S/yruKf46+OQJxAy5E4hEak=; b=mcZvlnlTjxDEMpsXVxgZHCis3EpF9YKEnl0Ae7vuyVNS2u5DsBmOpKu/RfyQY4zst4 WJ6II+4t9IB2/P5txc1C3I3Np7nADPSzcXWHbYbRQ5mjaMV/Q70uDa1eXdwLx4L/H1LE h2/Z87csKjZVXK2Jk3u43fy7aoYHA+l58kS+mcD5zTVL2tNNGwHuC6GbGWrQVIQ90jvt aa+QaAM01GJcJeenk3D8K0YFFYwl1QQfsaBPmiHcBmnF9TfXbkRBjff1fVlefRtMNNhn YS1V3p06jYuC6sbH3f2RCtKxaMrWYTkXD2GmUCqwfUvFV0t0KJruEDE5MJpqDswVGQ9H m6Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sqSfnQDS8sjUZN/3AxA8S/yruKf46+OQJxAy5E4hEak=; b=iWxF2D4NyzIAZ2rmflDNYmZ2uXwhkcsTj9CtrYy6x8hWMtG+C/KgynsN1hTtEb+Lui G3Uct2QbwPD4+brWaD7rTgxX9lB/DSzP6aCEO9BHV1J54eYu8LJTjPTJefi+EcswctkB o64uBhCHWzg/JrgpTg81vxKrY2Sll+CTLM7UVpKWAHIbaEH5wsaI/kw9JZC+2kFkK9pG CjWxtUBDbrwoE8pan83Cy9Q0Y0ZOTkWORHtE3IQcAAxkN9JB2mhMfqcCT4lNuIiHFflH FoeR6M+lUzq2FuXSo1Is1gTjg1LaajrNtl3TlYQZx77nsMOVA+TiDJMZwePw3fAvOIFH 4vYw== X-Gm-Message-State: APjAAAUUoxUN3AX4tVFD8qmKhB3JNEenBUwJX/j4qsZzoc96UbFhW3C5 otroOn5uQJMOnL5Rtq5iQEMbvHJZO4Y= X-Received: by 2002:a17:902:74c7:: with SMTP id f7mr5308584plt.263.1567078572662; Thu, 29 Aug 2019 04:36:12 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id e66sm6401987pfe.142.2019.08.29.04.36.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:12 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 30/44] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Date: Thu, 29 Aug 2019 17:04:15 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 06f1494f837da8997d670a1ba87add7963b08922 upstream. Some minor erratum may not be fixed in further revisions of a core, leading to a situation where the workaround needs to be updated each time an updated core is released. Introduce a MIDR_ALL_VERSIONS match helper that will work for all versions of that MIDR, once and for all. Acked-by: Thomas Gleixner Acked-by: Mark Rutland Acked-by: Daniel Lezcano Reviewed-by: Suzuki K Poulose Signed-off-by: Marc Zyngier Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpu_errata.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 19c51d1cd302..80765feae955 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -124,6 +124,13 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, .midr_range_min = min, \ .midr_range_max = max +#define MIDR_ALL_VERSIONS(model) \ + .def_scope = SCOPE_LOCAL_CPU, \ + .matches = is_affected_midr_range, \ + .midr_model = model, \ + .midr_range_min = 0, \ + .midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK) + const struct arm64_cpu_capabilities arm64_errata[] = { #if defined(CONFIG_ARM64_ERRATUM_826319) || \ defined(CONFIG_ARM64_ERRATUM_827319) || \