From patchwork Mon Sep 9 15:44:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 173393 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp4535365ilq; Mon, 9 Sep 2019 08:47:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqxcIuwjEwaZbDlbTKQ9CPp4+RZcb3V8cCmzK4hKXWBsDQHYUqq59bJIDijyWtfYVxzW73Zh X-Received: by 2002:aa7:d5cb:: with SMTP id d11mr25459100eds.250.1568044041220; Mon, 09 Sep 2019 08:47:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568044041; cv=none; d=google.com; s=arc-20160816; b=aetZNSbTU2/mzqnhTkquzspRFJpyCtDKmp2ZbvmF9U4xHLiWLYkd4204ySg5Ev/ocl xcAULWW3qfvIA1rjO4gktqnXFH4uERzR5jWcVvIEsEBNfdXVgai63Sp5hizIwyh3CXDA V/J91ecc0ldqwsmIT/Ljss0Sn8pWaXsWauKDSwG+Lrd9RQkKCllq2nL1uuKXWFXXOpII NB2gZNWffAB0m+6XctvupsRSElIoSPc9MDek3Po348j6XJUDh5sMTbVhhl4/bTmlD2iy o0zU2vEiCuXBi7c/2A0z//lmnNHANcrzrvHoJFHtl+MHeddsYKmYoDcG6bZ09qtPBRKf EH4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature:delivered-to:sender :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mailing-list:dkim-signature:domainkey-signature; bh=sHqBuws+U4sZgFQnPy0bOSp+RU+GMyPrGIvelY35shg=; b=F/pqdEB63dt9Wcs9h0huhYU+sRAjh5CzBONcDxtzrmzqw5xakkmc6WCR5cKLk3/KY4 uNmpToUdHYJ0hAHxRM6RXsAvgfyThd8BaSisEAwSvlLzCD2VUHkqBOGYvQYjyK/mkK1M 2BEh0W+NuKWnSfl6QiOxEUODFbcvIabteWqDlZYed5fLK6q21RMGN8VBNrCaHrZA3yfg hzRGjwBfJDXbNVciYC1yMMbjM2GbI9ibvIygNYKmAsC/cGojy/bEA5Tr0xBG1L0/j9de NVm0L+iZWIhzxt2MT2fA5NERiV2DWH0DKJPnouA+qqxze9Kd2Dqv7mcRdUBIBRQg2bvi zLrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=VLSpLou0; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=d9rZL8Ux; spf=pass (google.com: domain of gcc-patches-return-508646-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-508646-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id z11si2398737ejo.299.2019.09.09.08.47.20 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Sep 2019 08:47:21 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-508646-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=VLSpLou0; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=d9rZL8Ux; spf=pass (google.com: domain of gcc-patches-return-508646-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-508646-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references:mime-version :content-type:content-transfer-encoding; q=dns; s=default; b=jxi ZtM7wKz5IOa+2FJsL7Fvt1ab1lkvIGC1sO6PE3wV7dVui6JV3idj/VzCFgd5rVj4 rQGVpgXLfOVtkZKyRQdWE5865JgJRgByrrDwETJG2IiB9XXrHJR3Oh61fI4dUKpC ygRgzJFEfW6xBhLEXn1n2UR8Q/xYO5qnUQFnA858= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references:mime-version :content-type:content-transfer-encoding; s=default; bh=NNL9riMdb 1rsHc2+IMFb+3ZFyvA=; b=VLSpLou0NbQh/Cy+izNJoxkfPzawIe4h1hGetoGqv /LK39n0zU1V4r2/VKAiq9T3tZC72u1UkZYZ7+HCBF6UVMpEOj7OT7d3Z9sAyrV13 h4N2QL9OokLLtKsTTztcU0EE6ypTqGK0MQsJE4jQRjNEaX2j2Ci6axb2f/9EDhom k8= Received: (qmail 115094 invoked by alias); 9 Sep 2019 15:47:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 115086 invoked by uid 89); 9 Sep 2019 15:47:05 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_STOCKGEN, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy=rm X-HELO: mx07-00178001.pphosted.com Received: from mx07-00178001.pphosted.com (HELO mx07-00178001.pphosted.com) (62.209.51.94) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Sep 2019 15:47:01 +0000 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x89FkMTq001843 for ; Mon, 9 Sep 2019 17:46:58 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=STMicroelectronics; bh=sHqBuws+U4sZgFQnPy0bOSp+RU+GMyPrGIvelY35shg=; b=d9rZL8UxWRmlmCuyy4PDyWeu74e9ipRc0PHiGNPA2VWTkH7TQmUSkXzYChB7QViksnvH 8oUcZqGYA/4EXi8ms9SdF8VNctdDlqtyxQHw4E7sEDByASeYdeAsuSJeVRXb+Ko257S8 D5Ph0B25LdcWg/3G2Km0+VCREq7AmtNWYFWaFHMJcVgai+de6bJmX6jkUvMVoihEn0KV PqKWFUH/Aw5cuzvbPvXbVgCIj7a13FT0Q01pnLDoaBkzlN20Kx+itpR1vhXi7RDicOsQ ry2L9chiSJmRncX1ItFly9yp1gXUKIJmFSAGynt2DdTQT5xgiru66Q70fGChT8PgXADz 3A== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com with ESMTP id 2uv2avxh1j-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT) for ; Mon, 09 Sep 2019 17:46:57 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7C1484B for ; Mon, 9 Sep 2019 15:46:54 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node1.st.com [10.75.127.13]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id DC4A52B9BCB for ; Mon, 9 Sep 2019 17:46:53 +0200 (CEST) Received: from gnb.st.com (10.75.127.46) by SFHDAG5NODE1.st.com (10.75.127.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 9 Sep 2019 17:46:53 +0200 From: Christophe Lyon To: Subject: [ARM/FDPIC v6 04/24] [ARM] FDPIC: Add support for FDPIC for arm architecture Date: Mon, 9 Sep 2019 17:44:46 +0200 Message-ID: <20190909154526.11630-5-christophe.lyon@st.com> In-Reply-To: <20190909154526.11630-1-christophe.lyon@st.com> References: <20190909154526.11630-1-christophe.lyon@st.com> MIME-Version: 1.0 X-IsSubscribed: yes From: Christophe Lyon The FDPIC register is hard-coded to r9, as defined in the ABI. We have to disable tailcall optimizations if we don't know if the target function is in the same module. If not, we have to set r9 to the value associated with the target module. When generating a symbol address, we have to take into account whether it is a pointer to data or to a function, because different relocations are needed. 2019-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm-c.c (__FDPIC__): Define new pre-processor macro in FDPIC mode. * config/arm/arm-protos.h (arm_load_function_descriptor): Declare new function. * config/arm/arm.c (arm_option_override): Define pic register to FDPIC_REGNUM. (arm_function_ok_for_sibcall): Disable sibcall optimization if we have no decl or go through PLT. (calculate_pic_address_constant): New function. (legitimize_pic_address): Call calculate_pic_address_constant. (arm_load_pic_register): Handle TARGET_FDPIC. (arm_is_segment_info_known): New function. (arm_pic_static_addr): Add support for FDPIC. (arm_load_function_descriptor): New function. (arm_emit_call_insn): Add support for FDPIC. (arm_assemble_integer): Add support for FDPIC. * config/arm/arm.h (PIC_OFFSET_TABLE_REG_CALL_CLOBBERED): Define. (FDPIC_REGNUM): New define. * config/arm/arm.md (call): Add support for FDPIC. (call_value): Likewise. (restore_pic_register_after_call): New pattern. (untyped_call): Disable if FDPIC. (untyped_return): Likewise. * config/arm/unspecs.md (UNSPEC_PIC_RESTORE): New. gcc/testsuite/ * gcc.target/arm/fp16-aapcs-2.c: Adjust scan-assembler-times. * gcc.target/arm/fp16-aapcs-4.c: Likewise. Change-Id: I1e96d260074ab7b75d36cdff5d34ad898f35c66f -- 2.6.3 diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c index 6e256ee..34695fa 100644 --- a/gcc/config/arm/arm-c.c +++ b/gcc/config/arm/arm-c.c @@ -203,6 +203,8 @@ arm_cpu_builtins (struct cpp_reader* pfile) builtin_define ("__ARM_EABI__"); } + def_or_undef_macro (pfile, "__FDPIC__", TARGET_FDPIC); + def_or_undef_macro (pfile, "__ARM_ARCH_EXT_IDIV__", TARGET_IDIV); def_or_undef_macro (pfile, "__ARM_FEATURE_IDIV", TARGET_IDIV); diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 8386d89..f995974 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -139,6 +139,7 @@ extern int arm_max_const_double_inline_cost (void); extern int arm_const_double_inline_cost (rtx); extern bool arm_const_double_by_parts (rtx); extern bool arm_const_double_by_immediates (rtx); +extern rtx arm_load_function_descriptor (rtx funcdesc); extern void arm_emit_call_insn (rtx, rtx, bool); bool detect_cmse_nonsecure_call (tree); extern const char *output_call (rtx *); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 8576431..c34aab8 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3456,6 +3456,14 @@ arm_option_override (void) if (flag_pic && TARGET_VXWORKS_RTP) arm_pic_register = 9; + /* If in FDPIC mode then force arm_pic_register to be r9. */ + if (TARGET_FDPIC) + { + arm_pic_register = FDPIC_REGNUM; + if (TARGET_THUMB1) + sorry ("FDPIC mode is not supported in Thumb-1 mode"); + } + if (arm_pic_register_string != NULL) { int pic_register = decode_reg_name (arm_pic_register_string); @@ -7251,6 +7259,15 @@ arm_function_ok_for_sibcall (tree decl, tree exp) if (cfun->machine->sibcall_blocked) return false; + if (TARGET_FDPIC) + { + /* In FDPIC, never tailcall something for which we have no decl: + the target function could be in a different module, requiring + a different FDPIC register value. */ + if (decl == NULL) + return false; + } + /* Never tailcall something if we are generating code for Thumb-1. */ if (TARGET_THUMB1) return false; @@ -7461,6 +7478,24 @@ require_pic_register (rtx pic_reg, bool compute_now) } } +/* Generate insns to calculate the address of ORIG in pic mode. */ +static rtx_insn * +calculate_pic_address_constant (rtx reg, rtx pic_reg, rtx orig) +{ + rtx pat; + rtx mem; + + pat = gen_calculate_pic_address (reg, pic_reg, orig); + + /* Make the MEM as close to a constant as possible. */ + mem = SET_SRC (pat); + gcc_assert (MEM_P (mem) && !MEM_VOLATILE_P (mem)); + MEM_READONLY_P (mem) = 1; + MEM_NOTRAP_P (mem) = 1; + + return emit_insn (pat); +} + /* Legitimize PIC load to ORIG into REG. If REG is NULL, a new pseudo is created to hold the result of the load. If not NULL, PIC_REG indicates which register to use as PIC register, otherwise it is decided by register @@ -7505,24 +7540,13 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx reg, rtx pic_reg, insn = arm_pic_static_addr (orig, reg); else { - rtx pat; - rtx mem; - /* If this function doesn't have a pic register, create one now. */ require_pic_register (pic_reg, compute_now); if (pic_reg == NULL_RTX) pic_reg = cfun->machine->pic_reg; - pat = gen_calculate_pic_address (reg, pic_reg, orig); - - /* Make the MEM as close to a constant as possible. */ - mem = SET_SRC (pat); - gcc_assert (MEM_P (mem) && !MEM_VOLATILE_P (mem)); - MEM_READONLY_P (mem) = 1; - MEM_NOTRAP_P (mem) = 1; - - insn = emit_insn (pat); + insn = calculate_pic_address_constant (reg, pic_reg, orig); } /* Put a REG_EQUAL note on this insn, so that it can be optimized @@ -7677,7 +7701,9 @@ arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED, rtx pic_reg) { rtx l1, labelno, pic_tmp, pic_rtx; - if (crtl->uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) + if (crtl->uses_pic_offset_table == 0 + || TARGET_SINGLE_PIC_BASE + || TARGET_FDPIC) return; gcc_assert (flag_pic); @@ -7746,28 +7772,128 @@ arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED, rtx pic_reg) emit_use (pic_reg); } +/* Try to determine whether an object, referenced via ORIG, will be + placed in the text or data segment. This is used in FDPIC mode, to + decide which relocations to use when accessing ORIG. *IS_READONLY + is set to true if ORIG is a read-only location, false otherwise. + Return true if we could determine the location of ORIG, false + otherwise. *IS_READONLY is valid only when we return true. */ +static bool +arm_is_segment_info_known (rtx orig, bool *is_readonly) +{ + *is_readonly = false; + + if (GET_CODE (orig) == LABEL_REF) + { + *is_readonly = true; + return true; + } + + if (SYMBOL_REF_P (orig)) + { + if (CONSTANT_POOL_ADDRESS_P (orig)) + { + *is_readonly = true; + return true; + } + if (SYMBOL_REF_LOCAL_P (orig) + && !SYMBOL_REF_EXTERNAL_P (orig) + && SYMBOL_REF_DECL (orig) + && (!DECL_P (SYMBOL_REF_DECL (orig)) + || !DECL_COMMON (SYMBOL_REF_DECL (orig)))) + { + tree decl = SYMBOL_REF_DECL (orig); + tree init = (TREE_CODE (decl) == VAR_DECL) + ? DECL_INITIAL (decl) : (TREE_CODE (decl) == CONSTRUCTOR) + ? decl : 0; + int reloc = 0; + bool named_section, readonly; + + if (init && init != error_mark_node) + reloc = compute_reloc_for_constant (init); + + named_section = TREE_CODE (decl) == VAR_DECL + && lookup_attribute ("section", DECL_ATTRIBUTES (decl)); + readonly = decl_readonly_section (decl, reloc); + + /* We don't know where the link script will put a named + section, so return false in such a case. */ + if (named_section) + return false; + + *is_readonly = readonly; + return true; + } + + /* We don't know. */ + return false; + } + + gcc_unreachable (); +} + /* Generate code to load the address of a static var when flag_pic is set. */ static rtx_insn * arm_pic_static_addr (rtx orig, rtx reg) { rtx l1, labelno, offset_rtx; + rtx_insn *insn; gcc_assert (flag_pic); - /* We use an UNSPEC rather than a LABEL_REF because this label - never appears in the code stream. */ - labelno = GEN_INT (pic_labelno++); - l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); - l1 = gen_rtx_CONST (VOIDmode, l1); + bool is_readonly = false; + bool info_known = false; - /* On the ARM the PC register contains 'dot + 8' at the time of the - addition, on the Thumb it is 'dot + 4'. */ - offset_rtx = plus_constant (Pmode, l1, TARGET_ARM ? 8 : 4); - offset_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, orig, offset_rtx), - UNSPEC_SYMBOL_OFFSET); - offset_rtx = gen_rtx_CONST (Pmode, offset_rtx); + if (TARGET_FDPIC + && SYMBOL_REF_P (orig) + && !SYMBOL_REF_FUNCTION_P (orig)) + info_known = arm_is_segment_info_known (orig, &is_readonly); - return emit_insn (gen_pic_load_addr_unified (reg, offset_rtx, labelno)); + if (TARGET_FDPIC + && SYMBOL_REF_P (orig) + && !SYMBOL_REF_FUNCTION_P (orig) + && !info_known) + { + /* We don't know where orig is stored, so we have be + pessimistic and use a GOT relocation. */ + rtx pic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); + + insn = calculate_pic_address_constant (reg, pic_reg, orig); + } + else if (TARGET_FDPIC + && SYMBOL_REF_P (orig) + && (SYMBOL_REF_FUNCTION_P (orig) + || !is_readonly)) + { + /* We use the GOTOFF relocation. */ + rtx pic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); + + rtx l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, orig), UNSPEC_PIC_SYM); + emit_insn (gen_movsi (reg, l1)); + insn = emit_insn (gen_addsi3 (reg, reg, pic_reg)); + } + else + { + /* Not FDPIC, not SYMBOL_REF_P or readonly: we can use + PC-relative access. */ + /* We use an UNSPEC rather than a LABEL_REF because this label + never appears in the code stream. */ + labelno = GEN_INT (pic_labelno++); + l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); + l1 = gen_rtx_CONST (VOIDmode, l1); + + /* On the ARM the PC register contains 'dot + 8' at the time of the + addition, on the Thumb it is 'dot + 4'. */ + offset_rtx = plus_constant (Pmode, l1, TARGET_ARM ? 8 : 4); + offset_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, orig, offset_rtx), + UNSPEC_SYMBOL_OFFSET); + offset_rtx = gen_rtx_CONST (Pmode, offset_rtx); + + insn = emit_insn (gen_pic_load_addr_unified (reg, offset_rtx, + labelno)); + } + + return insn; } /* Return nonzero if X is valid as an ARM state addressing register. */ @@ -16051,9 +16177,32 @@ get_jump_table_size (rtx_jump_table_data *insn) return 0; } +/* Emit insns to load the function address from FUNCDESC (an FDPIC + function descriptor) into a register and the GOT address into the + FDPIC register, returning an rtx for the register holding the + function address. */ + +rtx +arm_load_function_descriptor (rtx funcdesc) +{ + rtx fnaddr_reg = gen_reg_rtx (Pmode); + rtx pic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); + rtx fnaddr = gen_rtx_MEM (Pmode, funcdesc); + rtx gotaddr = gen_rtx_MEM (Pmode, plus_constant (Pmode, funcdesc, 4)); + + emit_move_insn (fnaddr_reg, fnaddr); + + /* The ABI requires the entry point address to be loaded first, but + since we cannot support lazy binding for lack of atomic load of + two 32-bits values, we do not need to bother to prevent the + previous load from being moved after that of the GOT address. */ + emit_insn (gen_restore_pic_register_after_call (pic_reg, gotaddr)); + + return fnaddr_reg; +} + /* Return the maximum amount of padding that will be inserted before label LABEL. */ - static HOST_WIDE_INT get_label_padding (rtx label) { @@ -18188,6 +18337,12 @@ arm_emit_call_insn (rtx pat, rtx addr, bool sibcall) use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg); } + if (TARGET_FDPIC) + { + rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); + use_reg (&CALL_INSN_FUNCTION_USAGE (insn), fdpic_reg); + } + if (TARGET_AAPCS_BASED) { /* For AAPCS, IP and CC can be clobbered by veneers inserted by the @@ -23010,10 +23165,36 @@ arm_assemble_integer (rtx x, unsigned int size, int aligned_p) && (!SYMBOL_REF_LOCAL_P (x) || (SYMBOL_REF_DECL (x) ? DECL_WEAK (SYMBOL_REF_DECL (x)) : 0)))) - fputs ("(GOT)", asm_out_file); + { + if (TARGET_FDPIC && SYMBOL_REF_FUNCTION_P (x)) + fputs ("(GOTFUNCDESC)", asm_out_file); + else + fputs ("(GOT)", asm_out_file); + } else - fputs ("(GOTOFF)", asm_out_file); + { + if (TARGET_FDPIC && SYMBOL_REF_FUNCTION_P (x)) + fputs ("(GOTOFFFUNCDESC)", asm_out_file); + else + { + bool is_readonly; + + if (!TARGET_FDPIC + || arm_is_segment_info_known (x, &is_readonly)) + fputs ("(GOTOFF)", asm_out_file); + else + fputs ("(GOT)", asm_out_file); + } + } } + + /* For FDPIC we also have to mark symbol for .data section. */ + if (TARGET_FDPIC + && !making_const_table + && SYMBOL_REF_P (x) + && SYMBOL_REF_FUNCTION_P (x)) + fputs ("(FUNCDESC)", asm_out_file); + fputc ('\n', asm_out_file); return true; } diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 8b92c83..e404e2c 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -885,6 +885,9 @@ extern int arm_arch_cmse; Pascal), so the following is not true. */ #define STATIC_CHAIN_REGNUM 12 +/* r9 is the FDPIC register (base register for GOT and FUNCDESC accesses). */ +#define FDPIC_REGNUM 9 + /* Define this to be where the real frame pointer is if it is not possible to work out the offset between the frame pointer and the automatic variables until after register allocation has taken place. FRAME_POINTER_REGNUM @@ -1941,6 +1944,10 @@ extern unsigned arm_pic_register; data addresses in memory. */ #define PIC_OFFSET_TABLE_REGNUM arm_pic_register +/* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT + entries would need to handle saving and restoring it). */ +#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC + /* We can't directly access anything that contains a symbol, nor can we indirect via the constant pool. One exception is UNSPEC_TLS, which is always PIC. */ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index e236831..027febb 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -7601,6 +7601,11 @@ : !REG_P (callee)) XEXP (operands[0], 0) = force_reg (Pmode, callee); + if (TARGET_FDPIC && !SYMBOL_REF_P (XEXP (operands[0], 0))) + /* Indirect call: set r9 with FDPIC value of callee. */ + XEXP (operands[0], 0) + = arm_load_function_descriptor (XEXP (operands[0], 0)); + if (detect_cmse_nonsecure_call (addr)) { pat = gen_nonsecure_call_internal (operands[0], operands[1], @@ -7612,10 +7617,33 @@ pat = gen_call_internal (operands[0], operands[1], operands[2]); arm_emit_call_insn (pat, XEXP (operands[0], 0), false); } + + /* Restore FDPIC register (r9) after call. */ + if (TARGET_FDPIC) + { + rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); + rtx initial_fdpic_reg + = get_hard_reg_initial_val (Pmode, FDPIC_REGNUM); + + emit_insn (gen_restore_pic_register_after_call (fdpic_reg, + initial_fdpic_reg)); + } + DONE; }" ) +(define_insn "restore_pic_register_after_call" + [(set (match_operand:SI 0 "s_register_operand" "+r,r") + (unspec:SI [(match_dup 0) + (match_operand:SI 1 "nonimmediate_operand" "r,m")] + UNSPEC_PIC_RESTORE))] + "" + "@ + mov\t%0, %1 + ldr\t%0, %1" +) + (define_expand "call_internal" [(parallel [(call (match_operand 0 "memory_operand") (match_operand 1 "general_operand")) @@ -7689,6 +7717,11 @@ : !REG_P (callee)) XEXP (operands[1], 0) = force_reg (Pmode, callee); + if (TARGET_FDPIC && !SYMBOL_REF_P (XEXP (operands[1], 0))) + /* Indirect call: set r9 with FDPIC value of callee. */ + XEXP (operands[1], 0) + = arm_load_function_descriptor (XEXP (operands[1], 0)); + if (detect_cmse_nonsecure_call (addr)) { pat = gen_nonsecure_call_value_internal (operands[0], operands[1], @@ -7701,6 +7734,18 @@ operands[2], operands[3]); arm_emit_call_insn (pat, XEXP (operands[1], 0), false); } + + /* Restore FDPIC register (r9) after call. */ + if (TARGET_FDPIC) + { + rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); + rtx initial_fdpic_reg + = get_hard_reg_initial_val (Pmode, FDPIC_REGNUM); + + emit_insn (gen_restore_pic_register_after_call (fdpic_reg, + initial_fdpic_reg)); + } + DONE; }" ) @@ -8043,7 +8088,7 @@ (const_int 0)) (match_operand 1 "" "") (match_operand 2 "" "")])] - "TARGET_EITHER" + "TARGET_EITHER && !TARGET_FDPIC" " { int i; @@ -8110,7 +8155,7 @@ (define_expand "untyped_return" [(match_operand:BLK 0 "memory_operand") (match_operand 1 "" "")] - "TARGET_EITHER" + "TARGET_EITHER && !TARGET_FDPIC" " { int i; diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 41068ba..a9f99d0 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -89,6 +89,7 @@ UNSPEC_SP_SET ; Represent the setting of stack protector's canary UNSPEC_SP_TEST ; Represent the testing of stack protector's canary ; against the guard. + UNSPEC_PIC_RESTORE ; Use to restore fdpic register ]) (define_c_enum "unspec" [ diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c index 4753e36..51a76fc 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c +++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c @@ -17,5 +17,5 @@ F (__fp16 a, __fp16 b, __fp16 c) } /* { dg-final { scan-assembler-times {mov\tr[0-9]+, r[0-2]} 3 } } */ -/* { dg-final { scan-assembler-times {mov\tr1, r0} 1 } } */ +/* { dg-final { scan-assembler-times {mov\tr1, r[03]} 1 } } */ /* { dg-final { scan-assembler-times {mov\tr0, r[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c index 41c7ab7..ae65fb8 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c +++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c @@ -16,5 +16,5 @@ F (__fp16 a, __fp16 b, __fp16 c) } /* { dg-final { scan-assembler-times {mov\tr[0-9]+, r[0-2]} 3 } } */ -/* { dg-final { scan-assembler-times {mov\tr1, r0} 1 } } */ +/* { dg-final { scan-assembler-times {mov\tr1, r[03]} 1 } } */ /* { dg-final { scan-assembler-times {mov\tr0, r[0-9]+} 2 } } */