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[209.132.180.131]) by mx.google.com with ESMTPS id z21si8962132edc.4.2019.09.09.08.50.15 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Sep 2019 08:50:16 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-508655-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=FsImWl4Y; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b="1Q0Mr5a/"; spf=pass (google.com: domain of gcc-patches-return-508655-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-508655-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references:mime-version :content-type:content-transfer-encoding; q=dns; s=default; b=Iof xuGpBnqbWmmC/a47cPn95sQZXIO3U3SsHcdqecs8aaYc32sesYn5Rj2PFssXxp4C JQMSv5pGw9SssbZoKdQpOEpSHfeGtHs3NyMcEjATULoEBTQKuhH/txbdmXlpuoLO qXNMP93rWplumJ4ewk+AX0+c5S/Ri2IR5ZmeUJBk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references:mime-version :content-type:content-transfer-encoding; s=default; bh=dXIgCF8Jw yRGzkTKFQ5RWMUX0ck=; b=FsImWl4YNpfEnlYOOiEUHdJHDFz1y2jNxBOoxUOx+ aCKGUuYi/ycKyizwEUdLCV1er3XVyJ09g2rH2BRrupYAdLMvKzMoFwII8cIEYcUr kpz/xyHoKcnN4WG6rAyll8yyL/dZ2iiHzTrMtp7+kQUyun+ZrdsAVhpkqBseGBEq aA= Received: (qmail 128886 invoked by alias); 9 Sep 2019 15:50:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 128878 invoked by uid 89); 9 Sep 2019 15:50:04 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx07-00178001.pphosted.com Received: from mx07-00178001.pphosted.com (HELO mx07-00178001.pphosted.com) (62.209.51.94) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Sep 2019 15:50:03 +0000 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x89FkORN001286 for ; Mon, 9 Sep 2019 17:50:01 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=STMicroelectronics; bh=1aQ9HGDT+5uBJnceRF5Eaa0gSSJ4x1oK08RWqcj5YXE=; b=1Q0Mr5a/mD9dSUNo/heQgKH6RysztXDbjpLZvmNkgGBHpwPqfu+lN9+NnOrWtPvm+9XX D82wfkUnZ+kV3pNG5y68RYVQIXlc4P1MbmlWtPR/sSsPEz9LonHUz00I0a8Lt93DPaLW yWMUN4MLl/yMxe3GMhSrxLnF8JmhU5tPqiP1Ps4U3nirmdX2xjtqJgG3iEvWdPHNbWg5 MHVl5BcUkgJBbW9++PFzCQCpyueJQovAe6ov6cvWzT+tkAigSZkSNMPs/qn/l/cl/fI9 60GwlxgaGZbFtJRZSSrtvDnIDb9evVB1OuuGLngjH34IsutmkPqzlnbmtrI/gKueJ0qf Ww== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com with ESMTP id 2uv212ekn9-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT) for ; Mon, 09 Sep 2019 17:50:01 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 397F24B for ; Mon, 9 Sep 2019 15:49:56 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node1.st.com [10.75.127.13]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9941A2B9BFC for ; Mon, 9 Sep 2019 17:49:55 +0200 (CEST) Received: from gnb.st.com (10.75.127.46) by SFHDAG5NODE1.st.com (10.75.127.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 9 Sep 2019 17:49:55 +0200 From: Christophe Lyon To: Subject: [ARM/FDPIC v6 13/24] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture Date: Mon, 9 Sep 2019 17:44:55 +0200 Message-ID: <20190909154526.11630-14-christophe.lyon@st.com> In-Reply-To: <20190909154526.11630-1-christophe.lyon@st.com> References: <20190909154526.11630-1-christophe.lyon@st.com> MIME-Version: 1.0 X-IsSubscribed: yes From: Christophe Lyon Without this, when we are unwinding across a signal frame we can jump to an even address which leads to an exception. This is needed in __gnu_persnality_sigframe_fdpic() when restoring the PC from the signal frame since the PC saved by the kernel has the LSB bit set to zero. 2019-XX-XX Christophe Lyon Mickaël Guêné libgcc/ * config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only architecture. Change-Id: Ie84de548226bcf1751e19a09e8f091fb3013ccea -- 2.6.3 diff --git a/libgcc/config/arm/unwind-arm.c b/libgcc/config/arm/unwind-arm.c index 9ba73e7..8313ee0 100644 --- a/libgcc/config/arm/unwind-arm.c +++ b/libgcc/config/arm/unwind-arm.c @@ -199,6 +199,11 @@ _Unwind_VRS_Result _Unwind_VRS_Set (_Unwind_Context *context, return _UVRSR_FAILED; vrs->core.r[regno] = *(_uw *) valuep; +#if defined(__thumb__) + /* Force LSB bit since we always run thumb code. */ + if (regno == R_PC) + vrs->core.r[regno] |= 1; +#endif return _UVRSR_OK; case _UVRSC_VFP: