From patchwork Tue Sep 24 14:35:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 174279 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp4236695ill; Tue, 24 Sep 2019 07:36:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqyEWcf0LgAZsiQCZEPRVP9S9gUvCB8zhIqNQKjFWrAGpLcg78vhWgIXSmysMNF51TcjURH7 X-Received: by 2002:aca:cfc9:: with SMTP id f192mr414675oig.26.1569335814535; Tue, 24 Sep 2019 07:36:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569335814; cv=none; d=google.com; s=arc-20160816; b=sBFN9P717JxPvifQ0ucIHux1mqPiKnOHd7SsMB03e34WAShLbXZeMfvaEDpETaLISJ 2qjN+qWSVTd1sknZ3gphNSVIr8oKjPi8YUvtsyl4KrAoh/oviEhX4A3ZfG0YmsKoAOc5 IdHTA+E4i9M61EjjMm+dAqn3+IHoJAd6BUgF1CYlUvxercKKYrDpYXryu0PJpHg/FGAo lRug+QiJTjnidXv2Xj0n5lseajjtRSMt5y6RSY886HY3Ba10t5ZZyuxHTbXE7xitBPHa Q149XTU9dcFN+ayVHHCt33cf6/qUw92R9NkBMjpsYZRngdkuRiWiIzqif+quUA3r5gYW U2xQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=1n6Z1Dj7II36VgT30gIppqhPDLHSgMVAaZ+iEmCPUDg=; b=DQqE5vSTlapsog0Yyaa/pDLpIOjxP/5CETqJZAYz4sSzfQHdyksKSygLSvDSKizVJf 0wQLi6OrBnI5QVHvmqSZwXcJsG1IYshEtrR4vxVyFTYEv0tCwPr4C2O1PqsGcRcXmiR/ BzKonmpfQpTN+oE6OazCV8uck806kE4CFFFT5KJ5zbUpV0iAJ0exJwlH432U4nKrQKnm RopwPIgaeI69Jfqktu6OmZqbRYYPtVMtUfoFumO2AwBdjX2+gVFcu53hVdmnCv2r/9nY /KbfMNo9hmwjniLJDrYPBeGnHkR/RpYhxSWltTFSKWqLY7IT5QZqRGJm46KejlFRXAji RjjA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id i5si2916577jac.120.2019.09.24.07.36.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 24 Sep 2019 07:36:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iCluX-0000QG-EM; Tue, 24 Sep 2019 14:35:25 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iCluW-0000Q9-3j for xen-devel@lists.xenproject.org; Tue, 24 Sep 2019 14:35:24 +0000 X-Inumbo-ID: 89c5708e-ded8-11e9-bf31-bc764e2007e4 Received: from foss.arm.com (unknown [217.140.110.172]) by localhost (Halon) with ESMTP id 89c5708e-ded8-11e9-bf31-bc764e2007e4; Tue, 24 Sep 2019 14:35:21 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5D5D31570; Tue, 24 Sep 2019 07:35:21 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AC1D53F59C; Tue, 24 Sep 2019 07:35:20 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 24 Sep 2019 15:35:14 +0100 Message-Id: <20190924143515.8810-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190924143515.8810-1-julien.grall@arm.com> References: <20190924143515.8810-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.13 v2 1/2] xen/arm: Implement workaround for Cortex A-57 and Cortex A72 AT speculate X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Both Cortex-A57 (erratum 1319537) and Cortex-A72 (erratum 1319367) can end with corrupt TLBs if they speculate an AT instruction while S1/S2 system registers in inconsistent state. The workaround is the same as for Cortex A-76 implemented by commit a18be06aca "xen/arm: Implement workaround for Cortex-A76 erratum 1165522", so it is only necessary to plumb in the cpuerrata framework. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v2: - Add missing | --- docs/misc/arm/silicon-errata.txt | 2 ++ xen/arch/arm/cpuerrata.c | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt index 6cd1366f15..11e5a9dcec 100644 --- a/docs/misc/arm/silicon-errata.txt +++ b/docs/misc/arm/silicon-errata.txt @@ -48,5 +48,7 @@ stable hypervisors. | ARM | Cortex-A57 | #852523 | N/A | | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | +| ARM | Cortex-A57 | #1319537 | N/A | +| ARM | Cortex-A72 | #1319367 | N/A | | ARM | Cortex-A76 | #1165522 | N/A | | ARM | MMU-500 | #842869 | N/A | diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 6f483b2d8d..da72b02442 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -481,6 +481,16 @@ static const struct arm_cpu_capabilities arm_errata[] = { .capability = ARM64_WORKAROUND_AT_SPECULATE, MIDR_RANGE(MIDR_CORTEX_A76, 0, 2 << MIDR_VARIANT_SHIFT), }, + { + .desc = "ARM erratum 1319537", + .capability = ARM64_WORKAROUND_AT_SPECULATE, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + }, + { + .desc = "ARM erratum 1319367", + .capability = ARM64_WORKAROUND_AT_SPECULATE, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + }, {}, };