clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU

Message ID 20191023074118.3012-1-m.szyprowski@samsung.com
State New
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Series
  • clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU
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Commit Message

Marek Szyprowski Oct. 23, 2019, 7:41 a.m.
G3D clocks require special handling of their parent bus clock during power
domain on/off sequences. Those clocks were not initially added to the
sub-CMU handler, because that time there was no open-source driver for the
G3D (MALI Panfrost) hardware module and it was not possible to test it.

This patch fixes this issue. Parent clock for G3D hardware block is now
properly preserved during G3D power domain on/off sequence. This restores
proper MALI Panfrost performance broken by commit 8686764fc071
("ARM: dts: exynos: Add G3D power domain to Exynos542x").

Reported-by: Marian Mihailescu <mihailescu2m@gmail.com>
Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

Tested-by: Marian Mihailescu <mihailescu2m@gmail.com>

---
 drivers/clk/samsung/clk-exynos5420.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

-- 
2.17.1

Comments

Krzysztof Kozlowski Oct. 23, 2019, 7:46 a.m. | #1
On Wed, Oct 23, 2019 at 09:41:18AM +0200, Marek Szyprowski wrote:
> G3D clocks require special handling of their parent bus clock during power

> domain on/off sequences. Those clocks were not initially added to the

> sub-CMU handler, because that time there was no open-source driver for the

> G3D (MALI Panfrost) hardware module and it was not possible to test it.

> 

> This patch fixes this issue. Parent clock for G3D hardware block is now

> properly preserved during G3D power domain on/off sequence. This restores

> proper MALI Panfrost performance broken by commit 8686764fc071

> ("ARM: dts: exynos: Add G3D power domain to Exynos542x").

> 

> Reported-by: Marian Mihailescu <mihailescu2m@gmail.com>

> Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver")

> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

> Tested-by: Marian Mihailescu <mihailescu2m@gmail.com>

> ---

>  drivers/clk/samsung/clk-exynos5420.c | 21 +++++++++++++++++++--

>  1 file changed, 19 insertions(+), 2 deletions(-)


Acked-by: Krzysztof Kozlowski <krzk@kernel.org>


Best regards,
Krzysztof
Sylwester Nawrocki Oct. 23, 2019, 1:03 p.m. | #2
On 10/23/19 09:41, Marek Szyprowski wrote:
> G3D clocks require special handling of their parent bus clock during power

> domain on/off sequences. Those clocks were not initially added to the

> sub-CMU handler, because that time there was no open-source driver for the

> G3D (MALI Panfrost) hardware module and it was not possible to test it.

> 

> This patch fixes this issue. Parent clock for G3D hardware block is now

> properly preserved during G3D power domain on/off sequence. This restores

> proper MALI Panfrost performance broken by commit 8686764fc071

> ("ARM: dts: exynos: Add G3D power domain to Exynos542x").

> 

> Reported-by: Marian Mihailescu <mihailescu2m@gmail.com>

> Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver")

> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

> Tested-by: Marian Mihailescu <mihailescu2m@gmail.com>


Applied, thanks.

Patch

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 7670cc596c74..dfa862d55246 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1172,8 +1172,6 @@  static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
 	GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
 			GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
 
-	GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
-
 	/* CDREX */
 	GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
 			GATE_BUS_CDREX0, 0, 0, 0),
@@ -1248,6 +1246,15 @@  static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
 	{ DIV2_RATIO0, 0, 0x30 },	/* DIV dout_gscl_blk_300 */
 };
 
+static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
+	GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
+};
+
+static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = {
+	{ GATE_IP_G3D, 0x3ff, 0x3ff },	/* G3D gates */
+	{ SRC_TOP5, 0, BIT(16) },	/* MUX mout_user_aclk_g3d */
+};
+
 static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
 	DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
 };
@@ -1320,6 +1327,14 @@  static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = {
 	.pd_name	= "GSC",
 };
 
+static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = {
+	.gate_clks	= exynos5x_g3d_gate_clks,
+	.nr_gate_clks	= ARRAY_SIZE(exynos5x_g3d_gate_clks),
+	.suspend_regs	= exynos5x_g3d_suspend_regs,
+	.nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs),
+	.pd_name	= "G3D",
+};
+
 static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {
 	.div_clks	= exynos5x_mfc_div_clks,
 	.nr_div_clks	= ARRAY_SIZE(exynos5x_mfc_div_clks),
@@ -1351,6 +1366,7 @@  static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
 static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
 	&exynos5x_disp_subcmu,
 	&exynos5x_gsc_subcmu,
+	&exynos5x_g3d_subcmu,
 	&exynos5x_mfc_subcmu,
 	&exynos5x_mscl_subcmu,
 };
@@ -1358,6 +1374,7 @@  static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
 static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
 	&exynos5x_disp_subcmu,
 	&exynos5x_gsc_subcmu,
+	&exynos5x_g3d_subcmu,
 	&exynos5x_mfc_subcmu,
 	&exynos5x_mscl_subcmu,
 	&exynos5800_mau_subcmu,