clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume

Message ID 20191025090201.30246-1-m.szyprowski@samsung.com
State New
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Series
  • clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume
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Commit Message

Marek Szyprowski Oct. 25, 2019, 9:02 a.m.
Properly save and restore all top PLL related configuration registers
during suspend/resume cycle. So far driver only handled EPLL and RPLL
clocks, all other were reset to default values after suspend/resume cycle.
This caused for example lower G3D (MALI Panfrost) performance after system
resume, even if performance governor has been selected.

Reported-by: Reported-by: Marian Mihailescu <mihailescu2m@gmail.com>
Fixes: 773424326b51 ("clk: samsung: exynos5420: add more registers to restore list")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 drivers/clk/samsung/clk-exynos5420.c | 6 ++++++
 1 file changed, 6 insertions(+)

-- 
2.17.1

Comments

Sylwester Nawrocki Oct. 25, 2019, 9:21 a.m. | #1
On 10/25/19 11:02, Marek Szyprowski wrote:
> Properly save and restore all top PLL related configuration registers

> during suspend/resume cycle. So far driver only handled EPLL and RPLL

> clocks, all other were reset to default values after suspend/resume cycle.

> This caused for example lower G3D (MALI Panfrost) performance after system

> resume, even if performance governor has been selected.

> 

> Reported-by: Reported-by: Marian Mihailescu <mihailescu2m@gmail.com>

> Fixes: 773424326b51 ("clk: samsung: exynos5420: add more registers to restore list")

> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>


Applied, thanks.

Patch

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index d2e06ce58fb5..0aca98492029 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -165,12 +165,18 @@  static const unsigned long exynos5x_clk_regs[] __initconst = {
 	GATE_BUS_CPU,
 	GATE_SCLK_CPU,
 	CLKOUT_CMU_CPU,
+	CPLL_CON0,
+	DPLL_CON0,
 	EPLL_CON0,
 	EPLL_CON1,
 	EPLL_CON2,
 	RPLL_CON0,
 	RPLL_CON1,
 	RPLL_CON2,
+	IPLL_CON0,
+	SPLL_CON0,
+	VPLL_CON0,
+	MPLL_CON0,
 	SRC_TOP0,
 	SRC_TOP1,
 	SRC_TOP2,