From patchwork Sun Oct 27 21:01:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 177871 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp2543982ill; Sun, 27 Oct 2019 14:24:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqwA4+jzASjvFQR1qEyZFJQXTetzYriCtKuo0bGCRhzdE8kRWaGzh8iRa9xwefmjfACxryBG X-Received: by 2002:aa7:d858:: with SMTP id f24mr14242543eds.142.1572211484526; Sun, 27 Oct 2019 14:24:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572211484; cv=none; d=google.com; s=arc-20160816; b=GWjSs0UikphBp9hJRzrWpbw+EppHUSujASG/Ntmp02OuB4HL3GWS+AdRJv/jHVvJdm YfXEGEudc6aCW/CPhShe4GIKoO2+6A0xTPIf4OW5+PwTj5NPHb1Khni+vYjDtdVxS+Jm Ic6Rw1NfhlKSmIIPWH5F2hZ6W+gY7EOpL4ltsmxQJT0MtSBlNRpNLKwqgZWTbn1Jn5GC V9Xh47PpOtmTLRJi95Jp01bNQc+NbxivpO+RW/T5p+ohAQUFRPm7IXMv7D2LgfFCSpTn wHQjY1XsadL6kDsXA0yr9b0S6cpbViysXgl3hKllt5M2fMG6UGPRa4y3JI1AvjCbZNgW EN0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dHkeSffgG/gq2XFtQenAAyxk0aW/bGOWr6qm/I/8JHU=; b=DQxRqTZj+xqPNhWtVFyzc2qHlRbXt5cKW4UWKmga+rfvKtm+VO2V/VuL+cecVQ9A82 dVzE4fOPAp6G/6+PTRa1S5ULaLxDlf6gA/vZs3e+O3gWvzpZQpuEVTXC1kdkaLq5p/9B FN8M86vEpKrqsY8K/C9JK4x/MJSKcZNvwQdzu1KLYn/hWOL3ZpZewkhWOIG9406duYw9 3kcbkJ93PE38ixxJxQWjf3/CLCHySKUTT/MhvOgdIIDqPIDOTLyrqriRM6WsWg1tTboV M/37m8alPvVTQWIvXZ2iuT2A8i5pQz2iPBkXgd0Atx65OOxZTsjqenuBqPvwTlkYQGxP KjOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=fw1NjhcB; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r15si5014787eji.5.2019.10.27.14.24.44; Sun, 27 Oct 2019 14:24:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=fw1NjhcB; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732578AbfJ0VYn (ORCPT + 14 others); Sun, 27 Oct 2019 17:24:43 -0400 Received: from mail.kernel.org ([198.145.29.99]:46388 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732573AbfJ0VYn (ORCPT ); Sun, 27 Oct 2019 17:24:43 -0400 Received: from localhost (100.50.158.77.rev.sfr.net [77.158.50.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id DC64D21726; Sun, 27 Oct 2019 21:24:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1572211482; bh=ZFe86N/EscxSwYeE7npBjjyYeCxyrwEyFWXFXK0cBM0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fw1NjhcBIaVbLPn8GQkBMnH8PBAbdR/hQHw+kAgnYNXZNiuNPrbrtE5sTjz1UpLzl dTb0l6RLUbh1Duq6Z+ZcSRYRpesfWA39A1j1zsqMIIAPiJ7X6Xm/aQ+gTt/Tvw02L4 blGiIxhp+Ln0RUmmSiUryQVRvcbNtfHtVDtgv+jU= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Marc Zyngier , Will Deacon Subject: [PATCH 5.3 166/197] arm64: Allow CAVIUM_TX2_ERRATUM_219 to be selected Date: Sun, 27 Oct 2019 22:01:24 +0100 Message-Id: <20191027203403.257696914@linuxfoundation.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027203351.684916567@linuxfoundation.org> References: <20191027203351.684916567@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 603afdc9438ac546181e843f807253d75d3dbc45 upstream. Allow the user to select the workaround for TX2-219, and update the silicon-errata.rst file to reflect this. Cc: Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Greg Kroah-Hartman --- Documentation/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 17 +++++++++++++++++ 2 files changed, 19 insertions(+) --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -107,6 +107,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Cavium | ThunderX2 SMMUv3| #126 | N/A | +----------------+-----------------+-----------------+-----------------------------+ +| Cavium | ThunderX2 Core | #219 | CAVIUM_TX2_ERRATUM_219 | ++----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | +----------------+-----------------+-----------------+-----------------------------+ --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -601,6 +601,23 @@ config CAVIUM_ERRATUM_30115 If unsure, say Y. +config CAVIUM_TX2_ERRATUM_219 + bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" + default y + help + On Cavium ThunderX2, a load, store or prefetch instruction between a + TTBR update and the corresponding context synchronizing operation can + cause a spurious Data Abort to be delivered to any hardware thread in + the CPU core. + + Work around the issue by avoiding the problematic code sequence and + trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The + trap handler performs the corresponding register access, skips the + instruction and ensures context synchronization by virtue of the + exception return. + + If unsure, say Y. + config QCOM_FALKOR_ERRATUM_1003 bool "Falkor E1003: Incorrect translation due to ASID change" default y