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[67.170.172.113]) by smtp.gmail.com with ESMTPSA id f12sm10880612pfn.152.2019.10.28.14.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 14:59:25 -0700 (PDT) From: John Stultz To: lkml Cc: Yu Chen , Greg Kroah-Hartman , Rob Herring , Mark Rutland , ShuFan Lee , Heikki Krogerus , Suzuki K Poulose , Chunfeng Yun , Felipe Balbi , Hans de Goede , Andy Shevchenko , Jun Li , Valentin Schneider , Jack Pham , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, John Stultz Subject: [PATCH v4 2/9] usb: dwc3: Execute GCTL Core Soft Reset while switch modes Date: Mon, 28 Oct 2019 21:59:12 +0000 Message-Id: <20191028215919.83697-3-john.stultz@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191028215919.83697-1-john.stultz@linaro.org> References: <20191028215919.83697-1-john.stultz@linaro.org> From: Yu Chen On the HiKey960, we need to do a GCTL soft reset when switching modes. Jack Pham also noted that in the Synopsys databook it mentions performing a GCTL CoreSoftReset when changing the PrtCapDir between device & host modes. So this patch always does a GCTL Core Soft Reset when changing the mode. Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Mark Rutland CC: ShuFan Lee Cc: Heikki Krogerus Cc: Suzuki K Poulose Cc: Chunfeng Yun Cc: Yu Chen Cc: Felipe Balbi Cc: Hans de Goede Cc: Andy Shevchenko Cc: Jun Li Cc: Valentin Schneider Cc: Jack Pham Cc: linux-usb@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Yu Chen Signed-off-by: John Stultz --- v3: Remove quirk conditional, as Jack Pham noted the Synopsis databook states this should be done generally. Also, at Jacks' suggestion, make the reset call before changing the prtcap direction. --- drivers/usb/dwc3/core.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.17.1 diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 999ce5e84d3c..a039e35ec7ad 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -112,6 +112,19 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) dwc->current_dr_role = mode; } +static void dwc3_gctl_core_soft_reset(struct dwc3 *dwc) +{ + u32 reg; + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg |= DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); +} + static void __dwc3_set_mode(struct work_struct *work) { struct dwc3 *dwc = work_to_dwc(work); @@ -154,6 +167,9 @@ static void __dwc3_set_mode(struct work_struct *work) spin_lock_irqsave(&dwc->lock, flags); + /* Execute a GCTL Core Soft Reset when switch mode */ + dwc3_gctl_core_soft_reset(dwc); + dwc3_set_prtcap(dwc, dwc->desired_dr_role); spin_unlock_irqrestore(&dwc->lock, flags);