diff mbox series

[v2,4/4] mtd: spi-nor: Add support for w25q256jw

Message ID 20191030090124.24900-5-manivannan.sadhasivam@linaro.org
State Accepted
Commit 4c42f63553d79295910f7b4efd5f6dc37fe1a2a5
Headers show
Series None | expand

Commit Message

Manivannan Sadhasivam Oct. 30, 2019, 9:01 a.m. UTC
Add MTD support for w25q256jw SPI NOR chip from Winbond. This chip
supports dual/quad I/O mode with 512 blocks of memory organized in
64KB sectors. In addition to this, there is also small 4KB sectors
available for flexibility. The device has been validated using Thor96
board.

Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: linux-mtd@lists.infradead.org
Signed-off-by: Darshak Patel <darshak.patel@einfochips.com>

[Mani: cleaned up for upstream]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

---
 drivers/mtd/spi-nor/spi-nor.c | 2 ++
 1 file changed, 2 insertions(+)

-- 
2.17.1

Comments

Tudor Ambarus Nov. 7, 2019, 12:30 p.m. UTC | #1
On 11/01/2019 06:09 PM, Manivannan Sadhasivam wrote:
>> On 11/01/2019 04:58 PM, Manivannan Sadhasivam wrote:

>>>>> Add MTD support for w25q256jw SPI NOR chip from Winbond. This chip

>>>>> supports dual/quad I/O mode with 512 blocks of memory organized in

>>>>> 64KB sectors. In addition to this, there is also small 4KB sectors

>>>>> available for flexibility. The device has been validated using Thor96

>>>>> board.

>>>>>

>>>>> Cc: Marek Vasut <marek.vasut@gmail.com>

>>>>> Cc: Tudor Ambarus <tudor.ambarus@microchip.com>

>>>>> Cc: David Woodhouse <dwmw2@infradead.org>

>>>>> Cc: Brian Norris <computersforpeace@gmail.com>

>>>>> Cc: Miquel Raynal <miquel.raynal@bootlin.com>

>>>>> Cc: Richard Weinberger <richard@nod.at>

>>>>> Cc: Vignesh Raghavendra <vigneshr@ti.com>

>>>>> Cc: linux-mtd@lists.infradead.org

>>>>> Signed-off-by: Darshak Patel <darshak.patel@einfochips.com>

>>>>> [Mani: cleaned up for upstream]

>>>> Can we keep Darshak's authorship? We usually change the author if we feel that

>>>> we made a significant change to what was originally published.

>>>>

>>>> If it's just about cosmetics, cleaning or rebase, you can specify what you did

>>>> after the author's S-o-b tag and then add your S-o-b, as you did above.

>>>>

>>> I'd suggest to keep Darshak's authorship since he did the actual change in

>>> the bsp. I have to clean it up before submitting upstream and I mentioned

>>> the same above.

>>>

>> Ok, I'll amend the author when applying, it will be Darshak.

>>

> Ah no. I was saying we should keep both of ours authorship. It shouldn't

> be an issue because we both are involved in the process.


There can be only one author in a patch, and multiple signers if needed:

Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date:   Wed Oct 30 14:31:24 2019 +0530

    mtd: spi-nor: Add support for w25q256jw
[cut]
    Signed-off-by: Darshak Patel <darshak.patel@einfochips.com>

    [Mani: cleaned up for upstream]
    Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>


Please read
https://www.kernel.org/doc/html/v5.3/process/submitting-patches.html, paragraph
11), and tell me if you want me to amend the author to keep Darshak's authorship
or you want to keep yours.
diff mbox series

Patch

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 1d8621d43160..2c25b371d9f0 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2482,6 +2482,8 @@  static const struct flash_info spi_nor_ids[] = {
 	{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512,
 			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512,
+			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
 			SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },