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[192.237.175.120]) by mx.google.com with ESMTPS id d62si7257886iog.25.2019.10.31.08.11.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 31 Oct 2019 08:11:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iQC5E-0006cZ-Jk; Thu, 31 Oct 2019 15:09:56 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iQC5D-0006bE-A4 for xen-devel@lists.xenproject.org; Thu, 31 Oct 2019 15:09:55 +0000 X-Inumbo-ID: 768f7188-fbf0-11e9-954c-12813bfff9fa Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 768f7188-fbf0-11e9-954c-12813bfff9fa; Thu, 31 Oct 2019 15:09:41 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 130AD64F; Thu, 31 Oct 2019 08:09:41 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (unknown [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2887C3F71E; Thu, 31 Oct 2019 08:09:40 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Thu, 31 Oct 2019 15:09:09 +0000 Message-Id: <20191031150922.22938-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191031150922.22938-1-julien.grall@arm.com> References: <20191031150922.22938-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.13 v4 06/19] xen/arm64: entry: Avoid open-coding interrupt flags X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: jgross@suse.com, Volodymyr Babchuk , Julien Grall , Stefano Stabellini , Julien Grall MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, the interrupts to mask/unmask are hardcoded in the code making more difficult to find out what's going on. A new series of short-hand specific to the file entry.S is now added. The name of the short-hands should tell which interrupts will be changed by the msr daif{set, clr} instructions. Take the opportunity to replace the hardcoded values with the new short-hands. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v3: - Add Stefano's reviewed-by Changes in v2: - Patch added --- xen/arch/arm/arm64/entry.S | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S index 3e41ba65b6..fac4655bb9 100644 --- a/xen/arch/arm/arm64/entry.S +++ b/xen/arch/arm/arm64/entry.S @@ -6,6 +6,24 @@ #include #include +#define IFLAGS_D_BIT 8 +#define IFLAGS_A_BIT 4 +#define IFLAGS_I_BIT 2 +#define IFLAGS_F_BIT 1 + +/* + * Short-hands to define the interrupts (D, A, I, F) + * + * _ means the interrupt state will not change + * X means the state of interrupt X will change + * + * To be used with msr daif{set, clr} only. + * + */ +#define IFLAGS__AI_ IFLAGS_A_BIT | IFLAGS_I_BIT +#define IFLAGS__A__ IFLAGS_A_BIT +#define IFLAGS___I_ IFLAGS_I_BIT + /* * Stack pushing/popping (register pairs only). Equivalent to store decrement * before, load increment after. @@ -338,7 +356,7 @@ guest_sync_slowpath: ALTERNATIVE("bl check_pending_vserror; cbnz x0, 1f", "nop; nop", SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT) - msr daifclr, #6 + msr daifclr, #IFLAGS__AI_ mov x0, sp bl do_trap_guest_sync 1: @@ -354,7 +372,7 @@ guest_irq: ALTERNATIVE("bl check_pending_vserror; cbnz x0, 1f", "nop; nop", SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT) - msr daifclr, #4 + msr daifclr, #IFLAGS__A__ mov x0, sp bl do_trap_irq 1: @@ -366,7 +384,7 @@ guest_fiq_invalid: guest_error: entry hyp=0, compat=0 - msr daifclr, #6 + msr daifclr, #IFLAGS__AI_ mov x0, sp bl do_trap_guest_serror exit hyp=0, compat=0 @@ -381,7 +399,7 @@ guest_sync_compat: ALTERNATIVE("bl check_pending_vserror; cbnz x0, 1f", "nop; nop", SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT) - msr daifclr, #6 + msr daifclr, #IFLAGS__AI_ mov x0, sp bl do_trap_guest_sync 1: @@ -397,7 +415,7 @@ guest_irq_compat: ALTERNATIVE("bl check_pending_vserror; cbnz x0, 1f", "nop; nop", SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT) - msr daifclr, #4 + msr daifclr, #IFLAGS__A__ mov x0, sp bl do_trap_irq 1: @@ -409,7 +427,7 @@ guest_fiq_invalid_compat: guest_error_compat: entry hyp=0, compat=1 - msr daifclr, #6 + msr daifclr, #IFLAGS__AI_ mov x0, sp bl do_trap_guest_serror exit hyp=0, compat=1 @@ -420,7 +438,7 @@ ENTRY(return_to_new_vcpu64) exit hyp=0, compat=0 return_from_trap: - msr daifset, #2 /* Mask interrupts */ + msr daifset, #IFLAGS___I_ /* Mask interrupts */ ldr x21, [sp, #UREGS_PC] /* load ELR */ ldr w22, [sp, #UREGS_CPSR] /* load SPSR */ @@ -471,7 +489,7 @@ check_pending_vserror: * SError, the EL2 error exception will happen after PSTATE.A * is cleared. */ - msr daifclr, #4 + msr daifclr, #IFLAGS__A__ /* * This is our single instruction exception window. A pending @@ -490,7 +508,7 @@ abort_guest_exit_start: .global abort_guest_exit_end abort_guest_exit_end: /* Mask PSTATE asynchronous abort bit, close the checking window. */ - msr daifset, #4 + msr daifset, #IFLAGS__A__ /* * Compare elr_el2 and the saved value to check whether we are