From patchwork Thu Jun 9 04:05:27 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Pitre X-Patchwork-Id: 1783 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.45.109) by localhost6.localdomain6 with IMAP4-SSL; 10 Jun 2011 20:11:40 -0000 Delivered-To: patches@linaro.org Received: by 10.52.181.10 with SMTP id ds10cs218347vdc; Wed, 8 Jun 2011 21:05:29 -0700 (PDT) Received: by 10.52.115.163 with SMTP id jp3mr345312vdb.187.1307592329305; Wed, 08 Jun 2011 21:05:29 -0700 (PDT) Received: from mail-qy0-f178.google.com (mail-qy0-f178.google.com [209.85.216.178]) by mx.google.com with ESMTPS id fs4si712659vbb.88.2011.06.08.21.05.29 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 08 Jun 2011 21:05:29 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.216.178 is neither permitted nor denied by best guess record for domain of nicolas.pitre@linaro.org) client-ip=209.85.216.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.216.178 is neither permitted nor denied by best guess record for domain of nicolas.pitre@linaro.org) smtp.mail=nicolas.pitre@linaro.org Received: by qyk2 with SMTP id 2so739494qyk.16 for ; Wed, 08 Jun 2011 21:05:28 -0700 (PDT) Received: by 10.229.65.73 with SMTP id h9mr130454qci.269.1307592328767; Wed, 08 Jun 2011 21:05:28 -0700 (PDT) Received: from xanadu.home (modemcable092.28-130-66.mc.videotron.ca [66.130.28.92]) by mx.google.com with ESMTPS id u15sm962576qcq.24.2011.06.08.21.05.28 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 08 Jun 2011 21:05:28 -0700 (PDT) Date: Thu, 9 Jun 2011 00:05:27 -0400 (EDT) From: Nicolas Pitre X-X-Sender: nico@xanadu.home To: patches@arm.linux.org.uk cc: patches@linaro.org Subject: ARM: zImage: fix Thumb2 breakage Message-ID: User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Commit af3e4fd37a "ARM: 6859/1: Add writethrough dcache support for ARM926EJS processor" broke Thumb2 compilation by omitting to maintain the wide encoding for the added branch instructions which made the ARM926EJ-S record smaller than expected, breaking the record walk code. Signed-off-by: Nicolas Pitre CC: Mark A. Greer PATCH FOLLOWS KernelVersion: v3.0-rc1 diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index f9da419..942fad9 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -691,9 +691,9 @@ proc_types: .word 0x41069260 @ ARM926EJ-S (v5TEJ) .word 0xff0ffff0 - b __arm926ejs_mmu_cache_on - b __armv4_mmu_cache_off - b __armv5tej_mmu_cache_flush + W(b) __arm926ejs_mmu_cache_on + W(b) __armv4_mmu_cache_off + W(b) __armv5tej_mmu_cache_flush .word 0x00007000 @ ARM7 IDs .word 0x0000f000