From patchwork Tue Nov 5 20:52:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 178558 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp1302418ilf; Tue, 5 Nov 2019 13:10:27 -0800 (PST) X-Google-Smtp-Source: APXvYqxhTezFyp+ZKo2+YjU4CCo0Z2yzCGn/JzFGk2FF1UGzIhnCGbekPxwHB9WMimlqqtc1CEi9 X-Received: by 2002:a17:906:12d3:: with SMTP id l19mr3940396ejb.165.1572988227343; Tue, 05 Nov 2019 13:10:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572988227; cv=none; d=google.com; s=arc-20160816; b=Qr9jn0HfP3/CAHgMyZPCKexwlyAxrt3z5WNuy1lxiMZ1rzvIEuIKSnY3rK+uKYK2Bl 6n3hWZuL5uJzpyFDZaZf7zeGy/MnYWtBLKpffpqC959qh4GEmp3DlbVW5PW49ZDiYRei +/v1IOlFT/7GQ0LLBxwy0N/LSO+pEav62mwjsK8KcPNe2k6cVDy395E52APuwnyhcUsI HCFyW/RGQDnm9NRR2jyS/QpSWwDV+1gUIPqr3Jdy/+usz75lAfjlUaCSZ2L3LaNRkJEj XkfW3wj/6ijCxmERNKzUkVGfjTDfcq025rNEdREc0QVKXxnwgMemoBsFbFU/SU1RrHRU h7Zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from; bh=eIS7F+FZaKSWXKNnpV01VaXFEjfq/HmiS/eWWeIXRzM=; b=PWAzGUC1HBbU99Cy4dLcFyP//rOVkY/O74rpL6mxHLQDOYSBuYAe3xuodoQ/xbISKd 720dipxMeVOqb6NgZGK9MAcKBNnzq0LVRb7aTMRZsHw0lOHLkN3JxRHK3eRXQh8PetWC 2Nrn4wgkJdLA65JxoEB0696GkrS93wWYTsrLkv+yIJFWKyx5jbUQU9OX0877oBMQkVLR GZvNAIqsxy9cOc4l665NgW/umXQdp987n3EpS3qvDp0ulZu15jkSPZMy2DZldPGmCoXZ jN8ToFXzSB8HNcGZvfDouxItjDuR1rNokjx+3Ang9yydFiOvqtHZsJT/Ybq5y2dzLz1B CkEg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q20si15099574ejt.360.2019.11.05.13.10.27 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Nov 2019 13:10:27 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Received: from localhost ([::1]:50098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iS65p-0005nb-PE for patch@linaro.org; Tue, 05 Nov 2019 16:10:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58751) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iS5pX-0001Du-Rj for qemu-devel@nongnu.org; Tue, 05 Nov 2019 15:53:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iS5pW-0002Pq-G3 for qemu-devel@nongnu.org; Tue, 05 Nov 2019 15:53:35 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:11280) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iS5pT-00023C-HD; Tue, 05 Nov 2019 15:53:31 -0500 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id xA5KpY9B078175; Tue, 5 Nov 2019 15:53:10 -0500 Received: from ppma01wdc.us.ibm.com (fd.55.37a9.ip4.static.sl-reverse.com [169.55.85.253]) by mx0a-001b2d01.pphosted.com with ESMTP id 2w3eh7bw57-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 05 Nov 2019 15:53:09 -0500 Received: from pps.filterd (ppma01wdc.us.ibm.com [127.0.0.1]) by ppma01wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id xA5KnxfU018313; Tue, 5 Nov 2019 20:53:11 GMT Received: from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com [9.57.198.28]) by ppma01wdc.us.ibm.com with ESMTP id 2w11e71772-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 05 Nov 2019 20:53:11 +0000 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xA5Kr7WA12779976 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 5 Nov 2019 20:53:07 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1DAC412405B; Tue, 5 Nov 2019 20:53:07 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0B1FA124062; Tue, 5 Nov 2019 20:53:07 +0000 (GMT) Received: from localhost (unknown [9.53.179.218]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP; Tue, 5 Nov 2019 20:53:07 +0000 (GMT) From: Michael Roth To: qemu-devel@nongnu.org Subject: [PATCH 35/55] hw/arm/boot.c: Set NSACR.{CP11, CP10} for NS kernel boots Date: Tue, 5 Nov 2019 14:52:23 -0600 Message-Id: <20191105205243.3766-36-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191105205243.3766-1-mdroth@linux.vnet.ibm.com> References: <20191105205243.3766-1-mdroth@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-11-05_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1911050170 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell If we're booting a Linux kernel directly into Non-Secure state on a CPU which has Secure state, then make sure we set the NSACR CP11 and CP10 bits, so that Non-Secure is allowed to access the FPU. Otherwise an AArch32 kernel will UNDEF as soon as it tries to use the FPU. It used to not matter that we didn't do this until commit fc1120a7f5f2d4b6, where we implemented actually honouring these NSACR bits. The problem only exists for CPUs where EL3 is AArch32; the equivalent AArch64 trap bits are in CPTR_EL3 and are "0 to not trap, 1 to trap", so the reset value of the register permits NS access, unlike NSACR. Fixes: fc1120a7f5 Fixes: https://bugs.launchpad.net/qemu/+bug/1844597 Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190920174039.3916-1-peter.maydell@linaro.org (cherry picked from commit ece628fcf69cbbd4b3efb6fbd203af07609467a2) Signed-off-by: Michael Roth --- hw/arm/boot.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index c2b89b3bb9..fc4e021a38 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -754,6 +754,8 @@ static void do_cpu_reset(void *opaque) (cs != first_cpu || !info->secure_board_setup)) { /* Linux expects non-secure state */ env->cp15.scr_el3 |= SCR_NS; + /* Set NSACR.{CP11,CP10} so NS can access the FPU */ + env->cp15.nsacr |= 3 << 10; } }