@@ -54,6 +54,33 @@ _secure_monitor:
movs pc, lr @ return to non-secure SVC
+/*
+ * Secondary CPUs start here and call the code for the core specific parts
+ * of the non-secure and HYP mode transition. The GIC distributor specific
+ * code has already been executed by a C function before.
+ * Then they go back to wfi and wait to be woken up by the kernel again.
+ */
+.globl _smp_pen
+_smp_pen:
+ mrs r0, cpsr
+ orr r0, r0, #0xc0
+ msr cpsr, r0 @ disable interrupts
+ ldr r1, =_start
+ mcr p15, 0, r1, c12, c0, 0 @ set VBAR
+
+ bl _nonsec_init
+
+ ldr r1, [r3, #0x0c] @ read GICD acknowledge
+ str r1, [r3, #0x10] @ write GICD EOI
+ adr r1, _smp_pen
+waitloop:
+ wfi
+ ldr r0, =CONFIG_SYSFLAGS_ADDR @ load start address
+ ldr r0, [r0]
+ cmp r0, r1 @ make sure we dont execute this code
+ beq waitloop @ again (due to a spurious wakeup)
+ mov pc, r0
+
#define lo(x) ((x) & 0xFFFF)
#define hi(x) ((x) >> 16)
@@ -97,6 +97,7 @@ int armv7_switch_nonsec(void);
/* defined in cpu/armv7/nonsec_virt.S */
void _nonsec_init(void);
+void _smp_pen(void);
#endif /* CONFIG_ARMV7_VIRT */
#endif /* ! __ASSEMBLY__ */
@@ -95,6 +95,21 @@ static int get_gic_base_address(char **gicdptr)
#endif
}
+static void kick_secondary_cpus(char *gicdptr)
+{
+ unsigned int *sysflags;
+
+ sysflags = (void *)CONFIG_SYSFLAGS_ADDR;
+#ifdef CONFIG_SYSFLAGS_NEED_CLEAR_BITS
+ sysflags[1] = (unsigned)-1;
+#endif
+ *sysflags = (uintptr_t)_smp_pen;
+ dmb();
+
+ /* now kick all CPUs (expect this one) by writing to GICD_SGIR */
+ writel(1U << 24, &gicdptr[GICD_SGIR]);
+}
+
int armv7_switch_nonsec(void)
{
unsigned int reg, ret;
@@ -130,7 +145,9 @@ int armv7_switch_nonsec(void)
for (i = 0; i <= itlinesnr; i++)
writel((unsigned)-1, &gicdptr[GICD_IGROUPRn + 4 * i]);
- /* call the non-sec switching code on this CPU */
+ kick_secondary_cpus(gicdptr);
+
+ /* call the non-sec switching code on this CPU also */
_nonsec_init();
return 0;
@@ -31,4 +31,7 @@
#include "vexpress_common.h"
#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca15x2_tc2"
+#define CONFIG_SYSFLAGS_ADDR 0x1c010030
+#define CONFIG_SYSFLAGS_NEED_CLEAR_BITS
+
#endif
Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure state also. So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address. The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. The address secondary cores jump to is board specific, we provide the value here for the Versatile Express board. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> --- arch/arm/cpu/armv7/nonsec_virt.S | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/armv7.h | 1 + arch/arm/lib/virt-v7.c | 19 ++++++++++++++++++- include/configs/vexpress_ca15_tc2.h | 3 +++ 4 files changed, 49 insertions(+), 1 deletion(-)