ARM: dts: dra7: fix cpsw mdio fck clock

Message ID 20191118122016.22215-1-grygorii.strashko@ti.com
State New
Headers show
Series
  • ARM: dts: dra7: fix cpsw mdio fck clock
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Commit Message

Grygorii Strashko Nov. 18, 2019, 12:20 p.m.
The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0)
is specified incorrectly, which is caused incorrect MDIO bus clock
configuration MDCLK. The correct CPSW MDIO functional clock is
gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it.

Fixes: commit 1faa415c9c6e ("ARM: dts: Add fck for cpsw mdio for omap variants")
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>

---
 arch/arm/boot/dts/dra7-l4.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.17.1

Comments

Tony Lindgren Nov. 18, 2019, 2:50 p.m. | #1
* Grygorii Strashko <grygorii.strashko@ti.com> [191118 12:20]:
> The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0)

> is specified incorrectly, which is caused incorrect MDIO bus clock

> configuration MDCLK. The correct CPSW MDIO functional clock is

> gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it.


OK. Is this dra7 only, or are the other mdio clocks changed in commit
1faa415c9c6e wrong too?

Regards,

Tony
Grygorii Strashko Nov. 18, 2019, 9:08 p.m. | #2
On 18/11/2019 16:50, Tony Lindgren wrote:
> * Grygorii Strashko <grygorii.strashko@ti.com> [191118 12:20]:

>> The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0)

>> is specified incorrectly, which is caused incorrect MDIO bus clock

>> configuration MDCLK. The correct CPSW MDIO functional clock is

>> gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it.

> 

> OK. Is this dra7 only, or are the other mdio clocks changed in commit

> 1faa415c9c6e wrong too?


only DRA7.

-- 
Best regards,
grygorii
Tony Lindgren Nov. 18, 2019, 9:10 p.m. | #3
* Grygorii Strashko <grygorii.strashko@ti.com> [191118 21:09]:
> 

> 

> On 18/11/2019 16:50, Tony Lindgren wrote:

> > * Grygorii Strashko <grygorii.strashko@ti.com> [191118 12:20]:

> > > The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0)

> > > is specified incorrectly, which is caused incorrect MDIO bus clock

> > > configuration MDCLK. The correct CPSW MDIO functional clock is

> > > gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it.

> > 

> > OK. Is this dra7 only, or are the other mdio clocks changed in commit

> > 1faa415c9c6e wrong too?

> 

> only DRA7.


OK thanks for confirming that.

Tony
Tony Lindgren Nov. 20, 2019, 5:42 p.m. | #4
* Grygorii Strashko <grygorii.strashko@ti.com> [191118 04:20]:
> The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0)

> is specified incorrectly, which is caused incorrect MDIO bus clock

> configuration MDCLK. The correct CPSW MDIO functional clock is

> gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it.


Thanks applying into omap-for-v5.5/dt.

Tony

Patch

diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index 2f3a19edc7af..f69df2d2b554 100644
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -3059,7 +3059,7 @@ 
 
 				davinci_mdio: mdio@1000 {
 					compatible = "ti,cpsw-mdio","ti,davinci_mdio";
-					clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
+					clocks = <&gmac_main_clk>;
 					clock-names = "fck";
 					#address-cells = <1>;
 					#size-cells = <0>;