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[54.225.227.206]) by mx.google.com with ESMTPS id j47si22016901eeo.170.2013.06.20.01.24.56 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 20 Jun 2013 01:24:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linaro-mm-sig-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Received: from localhost ([127.0.0.1] helo=ip-10-141-164-156.ec2.internal) by ip-10-141-164-156.ec2.internal with esmtp (Exim 4.76) (envelope-from ) id 1UpaAh-0002VX-IL; Thu, 20 Jun 2013 08:24:47 +0000 Received: from hqemgate04.nvidia.com ([216.228.121.35]) by ip-10-141-164-156.ec2.internal with esmtp (Exim 4.76) (envelope-from ) id 1UpaAf-0002VS-No for linaro-mm-sig@lists.linaro.org; Thu, 20 Jun 2013 08:24:45 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Thu, 20 Jun 2013 01:24:59 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 20 Jun 2013 01:23:05 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 20 Jun 2013 01:23:05 -0700 Received: from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.298.1; Thu, 20 Jun 2013 01:24:44 -0700 Received: from DEMAIL01.nvidia.com ([10.21.69.139]) by deemhub02.nvidia.com ([10.21.69.138]) with mapi; Thu, 20 Jun 2013 10:24:42 +0200 From: Hiroshi Doyu To: "nishanth.p@gmail.com" Date: Thu, 20 Jun 2013 10:24:39 +0200 Thread-Topic: [Linaro-mm-sig] [RFC 2/3] ARM: dma-mapping: Pass DMA attrs as IOMMU prot Thread-Index: Ac5tj5zNdjJRDV6XQ8usLBmDlgEYuQ== Message-ID: <20130620.112439.1330557591655135630.hdoyu@nvidia.com> References: <1371707384-30037-1-git-send-email-hdoyu@nvidia.com><1371707384-30037-3-git-send-email-hdoyu@nvidia.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-nvconfidentiality: public acceptlanguage: en-US MIME-Version: 1.0 Cc: "linux-tegra@vger.kernel.org" , "linaro-mm-sig@lists.linaro.org" , "iommu@lists.linux-foundation.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [Linaro-mm-sig] [RFC 2/3] ARM: dma-mapping: Pass DMA attrs as IOMMU prot X-BeenThere: linaro-mm-sig@lists.linaro.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: linaro-mm-sig-bounces@lists.linaro.org Sender: linaro-mm-sig-bounces@lists.linaro.org X-Gm-Message-State: ALoCoQlvC+ytRVjg8mEKBCIuiGv8IOpQD84YpGUtwiuN1MzWdlD1w3rK7cmSgIaSga4RBHQ7yatc X-Original-Sender: hdoyu@nvidia.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::22f is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Hi Nishanth, Nishanth Peethambaran wrote @ Thu, 20 Jun 2013 10:07:00 +0200: > It would be better to define a prot flag bit in iommu API and convert > the attrs to prot flag bit in dma-mapping aPI before calling the iommu > API. That's the 1st option. > On Thu, Jun 20, 2013 at 11:19 AM, Hiroshi Doyu wrote: .... > > @@ -1280,7 +1281,7 @@ ____iommu_create_mapping(struct device *dev, dma_addr_t *req, > > break; > > > > len = (j - i) << PAGE_SHIFT; > > - ret = iommu_map(mapping->domain, iova, phys, len, 0); > > + ret = iommu_map(mapping->domain, iova, phys, len, (int)attrs); > > Use dma_get_attr and translate the READ_ONLY attr to a new READ_ONLY > prot flag bit which needs to be defined in iommu.h Both DMA_ATTR_READ_ONLY and IOMMU_READ are just logical bit in their layers respectively and eventually it's converted to H/W dependent bit. If IOMMU is considered as one of specific case of DMA, sharing dma_attr between IOMMU and DMA may not be so bad. IIRC, ARM: dma-mapping API was implemented based on this concept(?). diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index d8f98b1..161a1b0 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -755,7 +755,7 @@ int iommu_domain_has_cap(struct iommu_domain *domain, EXPORT_SYMBOL_GPL(iommu_domain_has_cap); int iommu_map(struct iommu_domain *domain, unsigned long iova, - phys_addr_t paddr, size_t size, int prot) + phys_addr_t paddr, size_t size, struct dma_attr *attrs) { unsigned long orig_iova = iova; unsigned int min_pagesz;