[v2,2/5] arm64: dts: qcom: qcs404: Add HFPLL node

Message ID 20191125142511.681149-3-niklas.cassel@linaro.org
State New
Headers show
Series
  • [v2,1/5] arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider
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Commit Message

Niklas Cassel Nov. 25, 2019, 2:25 p.m.
From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>


The high frequency pll functionality is required to enable CPU
frequency scaling operation.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

---
Changes since v1:
-None

 arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

-- 
2.23.0

Patch

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index f5f0c4c9cb16..78065fbb3626 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -904,6 +904,15 @@ 
 			#mbox-cells = <1>;
 		};
 
+		apcs_hfpll: clock-controller@b016000 {
+			compatible = "qcom,hfpll";
+			reg = <0x0b016000 0x30>;
+			#clock-cells = <0>;
+			clock-output-names = "apcs_hfpll";
+			clocks = <&xo_board>;
+			clock-names = "xo";
+		};
+
 		watchdog@b017000 {
 			compatible = "qcom,kpss-wdt";
 			reg = <0x0b017000 0x1000>;