[v2,2/5] dt-bindings: display: ti,am65x-dss: Add dt-schema yaml binding

Message ID 625fa000c744300b132d376dedf9b7ad83f6f2da.1575203210.git.jsarha@ti.com
State New
Headers show
Series
  • Untitled series #25330
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Commit Message

Jyri Sarha Dec. 1, 2019, 1:49 p.m.
Add dt-schema yaml bindig for AM65x DSS, AM65x version TI Keystone
Display SubSystem.

Signed-off-by: Jyri Sarha <jsarha@ti.com>

---
 .../bindings/display/ti/ti,am65x-dss.yaml     | 133 ++++++++++++++++++
 1 file changed, 133 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml

-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Patch

diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
new file mode 100644
index 000000000000..6691f5dad383
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
@@ -0,0 +1,133 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Texas Instruments AM65x Display Subsystem
+
+maintainers:
+  - Jyri Sarha <jsarha@ti.com>
+  - Tomi Valkeinen <tomi.valkeinen@ti.com>
+
+description: |
+  The AM65x TI Keystone Display SubSystem with two output ports and
+  two video planes. The first video port supports OLDI and the second
+  supports DPI format. The fist plane is full video plane with all
+  features and the second is a "lite plane" without scaling support.
+
+properties:
+  compatible:
+    const: ti,am65x-dss
+
+  reg:
+    maxItems: 7
+    minItems: 7
+
+  reg-names:
+    items:
+      - const: common
+      - const: vidl1
+      - const: vid
+      - const: ovr1
+      - const: ovr2
+      - const: vp1
+      - const: vp2
+
+  clocks:
+    maxItems: 3
+    minItems: 3
+
+  clock-names:
+    items:
+      - const: fck
+      - const: vp1
+      - const: vp2
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+    description: phandle to the associated power domain
+
+  port@0:
+    type: object
+    description:
+      The DSS OLDI output port node form video port 1
+
+  port@1:
+    type: object
+    description:
+      The DSS DPI output port node from video port 2
+
+  ti,am65x-oldi-io-ctrl:
+    maxItems: 1
+    description:
+      $ref: "/schemas/types.yaml#/definitions/phandle-array"
+      phandle to syscon device node mapping OLDI IO_CTRL registers.
+      The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
+      following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
+      and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
+      interface to work.
+
+  max-memory-bandwidth:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Input memory (from main memory to dispc) bandwidth limit in
+      bytes per second
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - interrupts
+  - "#address-cells"
+  - "#size-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+       dss: dss@04a00000 {
+                compatible = "ti,am65x-dss";
+                reg =   <0x0 0x04a00000 0x0 0x1000>, /* common */
+                        <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
+                        <0x0 0x04a06000 0x0 0x1000>, /* vid */
+                        <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
+                        <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
+                        <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
+                        <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
+                reg-names = "common", "vidl1", "vid",
+                        "ovr1", "ovr2", "vp1", "vp2";
+
+                ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
+
+                power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
+
+                clocks =        <&k3_clks 67 1>,
+                                <&k3_clks 216 1>,
+                                <&k3_clks 67 2>;
+                clock-names = "fck", "vp1", "vp2";
+
+                interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+
+                status = "disabled";
+
+                port@0 {
+                        reg = <0>;
+
+                        oldi_out0: endpoint {
+                                remote-endpoint = <&lcd_in0>;
+                        };
+                };
+        };