From patchwork Mon Dec 2 10:29:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 180585 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp5010673ile; Mon, 2 Dec 2019 02:29:55 -0800 (PST) X-Google-Smtp-Source: APXvYqwTr04aClEKIN1SQQikTexyLvtndvK3XsKHJbc3K7T39+GIctoiqM7eRM46IQKQL/7C9pQ1 X-Received: by 2002:a17:906:1d50:: with SMTP id o16mr14935428ejh.111.1575282594899; Mon, 02 Dec 2019 02:29:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575282594; cv=none; d=google.com; s=arc-20160816; b=1CkzPkXxSZS7kBFwfcU8jHBnn275b/7BsWloYv27qS1habeLLuR+zoGb5KQQkTAt79 DgZv5GmD2n/q8Fzkk2dQK46EyDy9cgz4dd0n/WM06PntWXPZ8pOgSeAdeDkEGSPbfAwc 8woziFQWJiFjVtdHfS3PPD792iqR5fJmpSZI68fGfJtaApDVIAI6qivjXpTD8tyuD+cG 0jUPIkt3yXP5WFauoK8oHDaJu7LE0PrcQtsbmtPk1aX0+9y4NRYxd886sh0eJ+SDe0V9 /BYJmxyUPpLNASLKlAo7sL6IvlsVi+PmmHiKQL0k2Rr+Z5G9WAVHaTaSxRIPRBBBndtx OyiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=rqmJ+MLUqIwO/rObser9An9b2bYpvXRp3EK9jFOMoLM=; b=CYW1qTlTGNB9gTcNg+BlH3Pl39eNJOSN/079GqGaEXWwfPV9n0GVKndmwgXN8eRaxZ Hkbk1Z43Ar8EW67b2pUuKcnWxBvEMZHJJcoMAZ9W9IL/0f9WEJeHPFhPnVfGOq6aSXF0 3eXR7rxOKmg+XosL+6dDcMnpBz9WATmw6oEa0PwKdGpJ3Qk+KX9U6qSPUcXQhA3uMtRj HvjdgJHXoJ7N6+AaOgjIHyfC12l4RDYdXSgcWI0CWe8xXPWmmwfXgJs0DJYC/ML5llXf S2fncEQxTAxKj3VQpbNt45bOPEALTbj5UzkG1iCCsJMzVoD/1QnZdB05DBqkJx8mXFMc P7XQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f9si20193873edy.221.2019.12.02.02.29.54; Mon, 02 Dec 2019 02:29:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727553AbfLBK3u (ORCPT + 27 others); Mon, 2 Dec 2019 05:29:50 -0500 Received: from mx2.suse.de ([195.135.220.15]:57520 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727378AbfLBK3W (ORCPT ); Mon, 2 Dec 2019 05:29:22 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id EEFA4B279; Mon, 2 Dec 2019 10:29:19 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v2 3/9] arm64: dts: realtek: rtd129x: Introduce r-bus Date: Mon, 2 Dec 2019 11:29:04 +0100 Message-Id: <20191202102910.26916-4-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191202102910.26916-1-afaerber@suse.de> References: <20191202102910.26916-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Model Realtek's register bus in DT. Signed-off-by: Andreas Färber --- v1 -> v2: * Fixed r-bus size from 0x100000 to 0x200000 (James) * Renamed node from r-bus to bus (Rob) arch/arm64/boot/dts/realtek/rtd129x.dtsi | 136 ++++++++++++++++--------------- 1 file changed, 72 insertions(+), 64 deletions(-) -- 2.16.4 diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi index 8d80cca945bc..5e755dda7abb 100644 --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi @@ -55,70 +55,78 @@ /* Exclude up to 2 GiB of RAM */ ranges = <0x80000000 0x80000000 0x80000000>; - reset1: reset-controller@98000000 { - compatible = "snps,dw-low-reset"; - reg = <0x98000000 0x4>; - #reset-cells = <1>; - }; - - reset2: reset-controller@98000004 { - compatible = "snps,dw-low-reset"; - reg = <0x98000004 0x4>; - #reset-cells = <1>; - }; - - reset3: reset-controller@98000008 { - compatible = "snps,dw-low-reset"; - reg = <0x98000008 0x4>; - #reset-cells = <1>; - }; - - reset4: reset-controller@98000050 { - compatible = "snps,dw-low-reset"; - reg = <0x98000050 0x4>; - #reset-cells = <1>; - }; - - iso_reset: reset-controller@98007088 { - compatible = "snps,dw-low-reset"; - reg = <0x98007088 0x4>; - #reset-cells = <1>; - }; - - wdt: watchdog@98007680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x98007680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@98007800 { - compatible = "snps,dw-apb-uart"; - reg = <0x98007800 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; - status = "disabled"; - }; - - uart1: serial@9801b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x9801b200 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR1>; - status = "disabled"; - }; - - uart2: serial@9801b400 { - compatible = "snps,dw-apb-uart"; - reg = <0x9801b400 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR2>; - status = "disabled"; + rbus: bus@98000000 { + compatible = "simple-bus"; + reg = <0x98000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000000 0x200000>; + + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; + + reset4: reset-controller@50 { + compatible = "snps,dw-low-reset"; + reg = <0x50 0x4>; + #reset-cells = <1>; + }; + + iso_reset: reset-controller@7088 { + compatible = "snps,dw-low-reset"; + reg = <0x7088 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@7680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x7680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + status = "disabled"; + }; + + uart1: serial@1b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR1>; + status = "disabled"; + }; + + uart2: serial@1b400 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b400 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR2>; + status = "disabled"; + }; }; gic: interrupt-controller@ff011000 {