[04/14] arm64: dts: realtek: rtd16xx: Introduce iso and misc syscon

Message ID 20191202182205.14629-5-afaerber@suse.de
State New
Headers show
Series
  • Untitled series #25353
Related show

Commit Message

Andreas Färber Dec. 2, 2019, 6:21 p.m.
Group UART0 into an Isolation syscon mfd node.
Group UART1 and UART2 into a Miscellaneous syscon mfd node.

Cc: James Tai <james.tai@realtek.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>

---
 arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 70 +++++++++++++++++++++-----------
 1 file changed, 46 insertions(+), 24 deletions(-)

-- 
2.16.4

Comments

James Tai Dec. 30, 2019, 5:53 a.m. | #1
> Group UART0 into an Isolation syscon mfd node.

> Group UART1 and UART2 into a Miscellaneous syscon mfd node.

> 

> Cc: James Tai <james.tai@realtek.com>

> Signed-off-by: Andreas Färber <afaerber@suse.de>

> ---

>  arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 70

> +++++++++++++++++++++-----------

>  1 file changed, 46 insertions(+), 24 deletions(-)

> 

> diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi

> b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi

> index 69cc0d941c8d..8f8f2b328cd1 100644

> --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi

> +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi

> @@ -118,34 +118,22 @@

>  			#size-cells = <1>;

>  			ranges = <0x0 0x98000000 0x200000>;

> 

> -			uart0: serial0@7800 {

> -				compatible = "snps,dw-apb-uart";

> -				reg = <0x7800 0x400>;

> -				reg-shift = <2>;

> +			iso: syscon@7000 {

> +				compatible = "syscon", "simple-mfd";

> +				reg = <0x7000 0x1000>;

>  				reg-io-width = <4>;

> -				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

> -				clock-frequency = <27000000>;

> -				status = "disabled";

> +				#address-cells = <1>;

> +				#size-cells = <1>;

> +				ranges = <0x0 0x7000 0x1000>;

>  			};

> 

> -			uart1: serial1@1b200 {

> -				compatible = "snps,dw-apb-uart";

> -				reg = <0x1b200 0x400>;

> -				reg-shift = <2>;

> +			misc: syscon@1b000 {

> +				compatible = "syscon", "simple-mfd";

> +				reg = <0x1b000 0x1000>;

>  				reg-io-width = <4>;

> -				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

> -				clock-frequency = <432000000>;

> -				status = "disabled";

> -			};

> -

> -			uart2: serial2@1b400 {

> -				compatible = "snps,dw-apb-uart";

> -				reg = <0x1b400 0x400>;

> -				reg-shift = <2>;

> -				reg-io-width = <4>;

> -				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;

> -				clock-frequency = <432000000>;

> -				status = "disabled";

> +				#address-cells = <1>;

> +				#size-cells = <1>;

> +				ranges = <0x0 0x1b000 0x1000>;

>  			};

>  		};

> 

> @@ -159,3 +147,37 @@

>  		};

>  	};

>  };

> +

> +&iso {

> +	uart0: serial0@800 {

> +		compatible = "snps,dw-apb-uart";

> +		reg = <0x800 0x400>;

> +		reg-shift = <2>;

> +		reg-io-width = <4>;

> +		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

> +		clock-frequency = <27000000>;

> +		status = "disabled";

> +	};

> +};

> +

> +&misc {

> +	uart1: serial1@200 {

> +		compatible = "snps,dw-apb-uart";

> +		reg = <0x200 0x400>;

> +		reg-shift = <2>;

> +		reg-io-width = <4>;

> +		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

> +		clock-frequency = <432000000>;

> +		status = "disabled";

> +	};

> +

> +	uart2: serial2@400 {

> +		compatible = "snps,dw-apb-uart";

> +		reg = <0x400 0x400>;

> +		reg-shift = <2>;

> +		reg-io-width = <4>;

> +		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;

> +		clock-frequency = <432000000>;

> +		status = "disabled";

> +	};

> +};

> --

> 2.16.4

> 

> 

Acked-by: James Tai <james.tai@realtek.com>

Patch

diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
index 69cc0d941c8d..8f8f2b328cd1 100644
--- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
@@ -118,34 +118,22 @@ 
 			#size-cells = <1>;
 			ranges = <0x0 0x98000000 0x200000>;
 
-			uart0: serial0@7800 {
-				compatible = "snps,dw-apb-uart";
-				reg = <0x7800 0x400>;
-				reg-shift = <2>;
+			iso: syscon@7000 {
+				compatible = "syscon", "simple-mfd";
+				reg = <0x7000 0x1000>;
 				reg-io-width = <4>;
-				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-				clock-frequency = <27000000>;
-				status = "disabled";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0x7000 0x1000>;
 			};
 
-			uart1: serial1@1b200 {
-				compatible = "snps,dw-apb-uart";
-				reg = <0x1b200 0x400>;
-				reg-shift = <2>;
+			misc: syscon@1b000 {
+				compatible = "syscon", "simple-mfd";
+				reg = <0x1b000 0x1000>;
 				reg-io-width = <4>;
-				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
-				clock-frequency = <432000000>;
-				status = "disabled";
-			};
-
-			uart2: serial2@1b400 {
-				compatible = "snps,dw-apb-uart";
-				reg = <0x1b400 0x400>;
-				reg-shift = <2>;
-				reg-io-width = <4>;
-				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-				clock-frequency = <432000000>;
-				status = "disabled";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0x1b000 0x1000>;
 			};
 		};
 
@@ -159,3 +147,37 @@ 
 		};
 	};
 };
+
+&iso {
+	uart0: serial0@800 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x800 0x400>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <27000000>;
+		status = "disabled";
+	};
+};
+
+&misc {
+	uart1: serial1@200 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x200 0x400>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <432000000>;
+		status = "disabled";
+	};
+
+	uart2: serial2@400 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x400 0x400>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <432000000>;
+		status = "disabled";
+	};
+};