From patchwork Mon Dec 2 18:22:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 180629 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp346102ile; Mon, 2 Dec 2019 10:22:28 -0800 (PST) X-Google-Smtp-Source: APXvYqx10gBMVSvkxFlJjLmrSRsmOhSnQREu0UfXfPoDpfbvGK7dg/pg0eDFTXpvS4tYF43ippfO X-Received: by 2002:a17:906:f28a:: with SMTP id gu10mr538058ejb.107.1575310947836; Mon, 02 Dec 2019 10:22:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575310947; cv=none; d=google.com; s=arc-20160816; b=YARpBMDT3NuSTFLNMnZ1NZiKrwyVk+9AT63PCslWZDv6onRWe0nvwBBAZKaad6op8u bZ3OzkbvFYfNI0o5cdNuJrbNrMvTrBRtgTgJANeIz6mugGMH5Lk557IxJMWOpQwb+ML/ 0AejA0Cwvju/h36CgJRoCDsmnSBt+DLgA8hZ/YbEeDMqfiW4Cf/KPvsRP7XrCzIWiu0u ZIoY6O+BBmu7vg+VdXFNmHdyWn/QsDkntS9T9NpRFWaD2JJtJ7eZTLJYqvf7JEwzgVLJ o0h7xvdIIUgmBUxQI4eo27y3kc1270oOh2hOQX0LIlfzi16OhPUgyQwefbicKFz+cVTo HUAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=KlHfTUd5EI9Uw8hbNt30oNOx6Jb4dgjpe7bnLAmiRaw=; b=T5+7oYKD6Sthl+BprlZYaKVGpESjHAqoAWKogX+WGzOgVB2z98LJBvH4e1m8oDUfiE OYekrlFvlHkwiMP2RfOyO9d8u9c1jmas+HPU1hzV8AKcpX7n1pJwAe+UCxvL+Y5M55yZ BSbbAW8mUSUZYWtJd3WlXABCvdRjQvCEw51HGcChmaUC5nK51HBzCWGfZVhyauT/uW9B QDFCNJ/ha1+bXgB8jQ9NpD8fL5hbRQfnNjwF9V8FDKm1UqnE6yjcIXcPrDVMKKtq7rEp zEDorj07MTeBB2mCSstyvJ6UvM6w5CEGXiaTE8GcFgg7+CwLnCju4K2FHEc5x7FpMFJv HB9A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f15si166290edy.159.2019.12.02.10.22.27; Mon, 02 Dec 2019 10:22:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727962AbfLBSWZ (ORCPT + 8 others); Mon, 2 Dec 2019 13:22:25 -0500 Received: from mx2.suse.de ([195.135.220.15]:36014 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727872AbfLBSWU (ORCPT ); Mon, 2 Dec 2019 13:22:20 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 6E725AD75; Mon, 2 Dec 2019 18:22:19 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Philipp Zabel , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 14/14] dt-bindings: reset: rtd1295: Add SB2 reset Date: Mon, 2 Dec 2019 19:22:04 +0100 Message-Id: <20191202182205.14629-15-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191202182205.14629-1-afaerber@suse.de> References: <20191202182205.14629-1-afaerber@suse.de> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a constant for reset3 SB2, based on downstream crt_sys_reg.h. Signed-off-by: Andreas Färber --- include/dt-bindings/reset/realtek,rtd1295.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.16.4 Acked-by: Rob Herring Acked-by: James Tai diff --git a/include/dt-bindings/reset/realtek,rtd1295.h b/include/dt-bindings/reset/realtek,rtd1295.h index 2c0cb6afe816..dd89e4c80264 100644 --- a/include/dt-bindings/reset/realtek,rtd1295.h +++ b/include/dt-bindings/reset/realtek,rtd1295.h @@ -75,6 +75,9 @@ #define RTD1295_RSTN_CBUS_TX 30 #define RTD1295_RSTN_SDS_PHY 31 +/* soft reset 3 */ +#define RTD1295_RSTN_SB2 0 + /* soft reset 4 */ #define RTD1295_RSTN_DCPHY_CRT 0 #define RTD1295_RSTN_DCPHY_ALERT_RX 1