[v4,04/40] target/arm: Add TTBR1_EL2

Message ID 20191203022937.1474-5-richard.henderson@linaro.org
State New
Headers show
Series
  • target/arm: Implement ARMv8.1-VHE
Related show

Commit Message

Richard Henderson Dec. 3, 2019, 2:29 a.m.
At the same time, add writefn to TTBR0_EL2 and TCR_EL2.
A later patch will update any ASID therein.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/helper.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

-- 
2.17.1

Comments

Laurent Desnogues Dec. 10, 2019, 9:14 a.m. | #1
Hi Richard,

On Tue, Dec 3, 2019 at 3:35 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> At the same time, add writefn to TTBR0_EL2 and TCR_EL2.

> A later patch will update any ASID therein.

>

> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/helper.c | 18 +++++++++++++-----

>  1 file changed, 13 insertions(+), 5 deletions(-)

>

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index b4d774632d..06ec4641f3 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -3484,6 +3484,12 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,

>      raw_write(env, ri, value);

>  }

>

> +static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,

> +                                    uint64_t value)

> +{

> +    raw_write(env, ri, value);

> +}

> +

>  static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,

>                          uint64_t value)

>  {

> @@ -4893,10 +4899,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {

>        .resetvalue = 0 },

>      { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,

>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,

> -      .access = PL2_RW,

> -      /* no .writefn needed as this can't cause an ASID change;

> -       * no .raw_writefn or .resetfn needed as we never use mask/base_mask

> -       */

> +      .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,


Are you sure you should call vmsa_tcr_ttbr_el2_write for a tcr_el2
write?  As far as I can see, tcr_el2 has no ASID field in bits
[63:48]. On the other hand there are various other bits in TCR_EL2
that might require a TLB flush; for instance the A1 bit [22] that
defines where to pick ASID from.

Thanks,

Laurent

> +      /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */

>        .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },

>      { .name = "VTCR", .state = ARM_CP_STATE_AA32,

>        .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,

> @@ -4930,7 +4934,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {

>        .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },

>      { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,

>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,

> -      .access = PL2_RW, .resetvalue = 0,

> +      .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write,

>        .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },

>      { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,

>        .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,

> @@ -6959,6 +6963,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)

>                .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,

>                .access = PL2_RW,

>                .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },

> +            { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,

> +              .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,

> +              .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,

> +              .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) },

>              REGINFO_SENTINEL

>          };

>          define_arm_cp_regs(cpu, vhe_reginfo);

> --

> 2.17.1

>

>

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index b4d774632d..06ec4641f3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3484,6 +3484,12 @@  static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     raw_write(env, ri, value);
 }
 
+static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                    uint64_t value)
+{
+    raw_write(env, ri, value);
+}
+
 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                         uint64_t value)
 {
@@ -4893,10 +4899,8 @@  static const ARMCPRegInfo el2_cp_reginfo[] = {
       .resetvalue = 0 },
     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
-      .access = PL2_RW,
-      /* no .writefn needed as this can't cause an ASID change;
-       * no .raw_writefn or .resetfn needed as we never use mask/base_mask
-       */
+      .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
+      /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
     { .name = "VTCR", .state = ARM_CP_STATE_AA32,
       .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
@@ -4930,7 +4934,7 @@  static const ARMCPRegInfo el2_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .resetvalue = 0,
+      .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write,
       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
@@ -6959,6 +6963,10 @@  void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
               .access = PL2_RW,
               .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
+            { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
+              .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
+              .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
+              .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) },
             REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, vhe_reginfo);