[v4,16/40] target/arm: Rearrange ARMMMUIdxBit

Message ID 20191203022937.1474-17-richard.henderson@linaro.org
State New
Headers show
Series
  • target/arm: Implement ARMv8.1-VHE
Related show

Commit Message

Richard Henderson Dec. 3, 2019, 2:29 a.m.
Define via macro expansion, so that renumbering of the base ARMMMUIdx
symbols is automatically reflexed in the bit definitions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/cpu.h | 39 +++++++++++++++++++++++----------------
 1 file changed, 23 insertions(+), 16 deletions(-)

-- 
2.17.1

Comments

Alex Bennée Dec. 4, 2019, 11:56 a.m. | #1
Richard Henderson <richard.henderson@linaro.org> writes:

> Define via macro expansion, so that renumbering of the base ARMMMUIdx

> symbols is automatically reflexed in the bit definitions.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


> ---

>  target/arm/cpu.h | 39 +++++++++++++++++++++++----------------

>  1 file changed, 23 insertions(+), 16 deletions(-)

>

> diff --git a/target/arm/cpu.h b/target/arm/cpu.h

> index 5f295c7e60..6ba5126852 100644

> --- a/target/arm/cpu.h

> +++ b/target/arm/cpu.h

> @@ -2886,27 +2886,34 @@ typedef enum ARMMMUIdx {

>      ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,

>  } ARMMMUIdx;

>  

> -/* Bit macros for the core-mmu-index values for each index,

> +/*

> + * Bit macros for the core-mmu-index values for each index,

>   * for use when calling tlb_flush_by_mmuidx() and friends.

>   */

> +#define TO_CORE_BIT(NAME) \

> +    ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)

> +

>  typedef enum ARMMMUIdxBit {

> -    ARMMMUIdxBit_EL10_0 = 1 << 0,

> -    ARMMMUIdxBit_EL10_1 = 1 << 1,

> -    ARMMMUIdxBit_E2 = 1 << 2,

> -    ARMMMUIdxBit_SE3 = 1 << 3,

> -    ARMMMUIdxBit_SE0 = 1 << 4,

> -    ARMMMUIdxBit_SE1 = 1 << 5,

> -    ARMMMUIdxBit_Stage2 = 1 << 6,

> -    ARMMMUIdxBit_MUser = 1 << 0,

> -    ARMMMUIdxBit_MPriv = 1 << 1,

> -    ARMMMUIdxBit_MUserNegPri = 1 << 2,

> -    ARMMMUIdxBit_MPrivNegPri = 1 << 3,

> -    ARMMMUIdxBit_MSUser = 1 << 4,

> -    ARMMMUIdxBit_MSPriv = 1 << 5,

> -    ARMMMUIdxBit_MSUserNegPri = 1 << 6,

> -    ARMMMUIdxBit_MSPrivNegPri = 1 << 7,

> +    TO_CORE_BIT(EL10_0),

> +    TO_CORE_BIT(EL10_1),

> +    TO_CORE_BIT(E2),

> +    TO_CORE_BIT(SE0),

> +    TO_CORE_BIT(SE1),

> +    TO_CORE_BIT(SE3),

> +    TO_CORE_BIT(Stage2),

> +

> +    TO_CORE_BIT(MUser),

> +    TO_CORE_BIT(MPriv),

> +    TO_CORE_BIT(MUserNegPri),

> +    TO_CORE_BIT(MPrivNegPri),

> +    TO_CORE_BIT(MSUser),

> +    TO_CORE_BIT(MSPriv),

> +    TO_CORE_BIT(MSUserNegPri),

> +    TO_CORE_BIT(MSPrivNegPri),

>  } ARMMMUIdxBit;

>  

> +#undef TO_CORE_BIT

> +

>  #define MMU_USER_IDX 0

>  

>  static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)



-- 
Alex Bennée
Philippe Mathieu-Daudé Dec. 4, 2019, 4:01 p.m. | #2
On 12/3/19 3:29 AM, Richard Henderson wrote:
> Define via macro expansion, so that renumbering of the base ARMMMUIdx

> symbols is automatically reflexed in the bit definitions.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>   target/arm/cpu.h | 39 +++++++++++++++++++++++----------------

>   1 file changed, 23 insertions(+), 16 deletions(-)

> 

> diff --git a/target/arm/cpu.h b/target/arm/cpu.h

> index 5f295c7e60..6ba5126852 100644

> --- a/target/arm/cpu.h

> +++ b/target/arm/cpu.h

> @@ -2886,27 +2886,34 @@ typedef enum ARMMMUIdx {

>       ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,

>   } ARMMMUIdx;

>   

> -/* Bit macros for the core-mmu-index values for each index,

> +/*

> + * Bit macros for the core-mmu-index values for each index,

>    * for use when calling tlb_flush_by_mmuidx() and friends.

>    */

> +#define TO_CORE_BIT(NAME) \

> +    ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)

> +

>   typedef enum ARMMMUIdxBit {

> -    ARMMMUIdxBit_EL10_0 = 1 << 0,

> -    ARMMMUIdxBit_EL10_1 = 1 << 1,

> -    ARMMMUIdxBit_E2 = 1 << 2,

> -    ARMMMUIdxBit_SE3 = 1 << 3,

> -    ARMMMUIdxBit_SE0 = 1 << 4,

> -    ARMMMUIdxBit_SE1 = 1 << 5,

> -    ARMMMUIdxBit_Stage2 = 1 << 6,

> -    ARMMMUIdxBit_MUser = 1 << 0,

> -    ARMMMUIdxBit_MPriv = 1 << 1,

> -    ARMMMUIdxBit_MUserNegPri = 1 << 2,

> -    ARMMMUIdxBit_MPrivNegPri = 1 << 3,

> -    ARMMMUIdxBit_MSUser = 1 << 4,

> -    ARMMMUIdxBit_MSPriv = 1 << 5,

> -    ARMMMUIdxBit_MSUserNegPri = 1 << 6,

> -    ARMMMUIdxBit_MSPrivNegPri = 1 << 7,

> +    TO_CORE_BIT(EL10_0),

> +    TO_CORE_BIT(EL10_1),

> +    TO_CORE_BIT(E2),

> +    TO_CORE_BIT(SE0),

> +    TO_CORE_BIT(SE1),

> +    TO_CORE_BIT(SE3),

> +    TO_CORE_BIT(Stage2),

> +

> +    TO_CORE_BIT(MUser),

> +    TO_CORE_BIT(MPriv),

> +    TO_CORE_BIT(MUserNegPri),

> +    TO_CORE_BIT(MPrivNegPri),

> +    TO_CORE_BIT(MSUser),

> +    TO_CORE_BIT(MSPriv),

> +    TO_CORE_BIT(MSUserNegPri),

> +    TO_CORE_BIT(MSPrivNegPri),

>   } ARMMMUIdxBit;

>   

> +#undef TO_CORE_BIT

> +

>   #define MMU_USER_IDX 0

>   

>   static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)

> 


Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5f295c7e60..6ba5126852 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2886,27 +2886,34 @@  typedef enum ARMMMUIdx {
     ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
 } ARMMMUIdx;
 
-/* Bit macros for the core-mmu-index values for each index,
+/*
+ * Bit macros for the core-mmu-index values for each index,
  * for use when calling tlb_flush_by_mmuidx() and friends.
  */
+#define TO_CORE_BIT(NAME) \
+    ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
+
 typedef enum ARMMMUIdxBit {
-    ARMMMUIdxBit_EL10_0 = 1 << 0,
-    ARMMMUIdxBit_EL10_1 = 1 << 1,
-    ARMMMUIdxBit_E2 = 1 << 2,
-    ARMMMUIdxBit_SE3 = 1 << 3,
-    ARMMMUIdxBit_SE0 = 1 << 4,
-    ARMMMUIdxBit_SE1 = 1 << 5,
-    ARMMMUIdxBit_Stage2 = 1 << 6,
-    ARMMMUIdxBit_MUser = 1 << 0,
-    ARMMMUIdxBit_MPriv = 1 << 1,
-    ARMMMUIdxBit_MUserNegPri = 1 << 2,
-    ARMMMUIdxBit_MPrivNegPri = 1 << 3,
-    ARMMMUIdxBit_MSUser = 1 << 4,
-    ARMMMUIdxBit_MSPriv = 1 << 5,
-    ARMMMUIdxBit_MSUserNegPri = 1 << 6,
-    ARMMMUIdxBit_MSPrivNegPri = 1 << 7,
+    TO_CORE_BIT(EL10_0),
+    TO_CORE_BIT(EL10_1),
+    TO_CORE_BIT(E2),
+    TO_CORE_BIT(SE0),
+    TO_CORE_BIT(SE1),
+    TO_CORE_BIT(SE3),
+    TO_CORE_BIT(Stage2),
+
+    TO_CORE_BIT(MUser),
+    TO_CORE_BIT(MPriv),
+    TO_CORE_BIT(MUserNegPri),
+    TO_CORE_BIT(MPrivNegPri),
+    TO_CORE_BIT(MSUser),
+    TO_CORE_BIT(MSPriv),
+    TO_CORE_BIT(MSUserNegPri),
+    TO_CORE_BIT(MSPrivNegPri),
 } ARMMMUIdxBit;
 
+#undef TO_CORE_BIT
+
 #define MMU_USER_IDX 0
 
 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)