[v4,15/40] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits

Message ID 20191203022937.1474-16-richard.henderson@linaro.org
State New
Headers show
Series
  • target/arm: Implement ARMv8.1-VHE
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Commit Message

Richard Henderson Dec. 3, 2019, 2:29 a.m.
We are about to expand the number of mmuidx to 10, and so need 4 bits.
For the benefit of reading the number out of -d exec, align it to the
penultimate nibble.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/cpu.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

-- 
2.17.1

Comments

Alex Bennée Dec. 4, 2019, 11:48 a.m. | #1
Richard Henderson <richard.henderson@linaro.org> writes:

> We are about to expand the number of mmuidx to 10, and so need 4 bits.

> For the benefit of reading the number out of -d exec, align it to the

> penultimate nibble.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


> ---

>  target/arm/cpu.h | 12 ++++++------

>  1 file changed, 6 insertions(+), 6 deletions(-)

>

> diff --git a/target/arm/cpu.h b/target/arm/cpu.h

> index ae9fc1ded3..5f295c7e60 100644

> --- a/target/arm/cpu.h

> +++ b/target/arm/cpu.h

> @@ -3176,17 +3176,17 @@ typedef ARMCPU ArchCPU;

>   * Unless otherwise noted, these bits are cached in env->hflags.

>   */

>  FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)

> -FIELD(TBFLAG_ANY, MMUIDX, 28, 3)

> -FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1)

> -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1)     /* Not cached. */

> +FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)

> +FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1)     /* Not cached. */

> +FIELD(TBFLAG_ANY, BE_DATA, 28, 1)

> +FIELD(TBFLAG_ANY, MMUIDX, 24, 4)

>  /* Target EL if we take a floating-point-disabled exception */

> -FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)

> -FIELD(TBFLAG_ANY, BE_DATA, 23, 1)

> +FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)

>  /*

>   * For A-profile only, target EL for debug exceptions.

>   * Note that this overlaps with the M-profile-only HANDLER and STACKCHECK bits.

>   */

> -FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2)

> +FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)

>  

>  /*

>   * Bit usage when in AArch32 state, both A- and M-profile.



-- 
Alex Bennée

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ae9fc1ded3..5f295c7e60 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3176,17 +3176,17 @@  typedef ARMCPU ArchCPU;
  * Unless otherwise noted, these bits are cached in env->hflags.
  */
 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
-FIELD(TBFLAG_ANY, MMUIDX, 28, 3)
-FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1)
-FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1)     /* Not cached. */
+FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
+FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1)     /* Not cached. */
+FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
+FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
 /* Target EL if we take a floating-point-disabled exception */
-FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)
-FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
+FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
 /*
  * For A-profile only, target EL for debug exceptions.
  * Note that this overlaps with the M-profile-only HANDLER and STACKCHECK bits.
  */
-FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2)
+FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
 
 /*
  * Bit usage when in AArch32 state, both A- and M-profile.