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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 29/40] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Date: Mon, 2 Dec 2019 18:29:26 -0800 Message-Id: <20191203022937.1474-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since we only support a single ASID, flush the tlb when it changes. Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 9df55a8d6b..2a4d4c2c0d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3740,6 +3740,15 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + /* + * If we are running with E2&0 regime, then the ASID is active. + * Flush if that changes. + */ + if ((arm_hcr_el2_eff(env) & HCR_E2H) && + extract64(raw_read(env, ri) ^ value, 48, 16)) { + tlb_flush_by_mmuidx(env_cpu(env), + ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0); + } raw_write(env, ri, value); }