[10/11] target/arm: Implement ATS1E1 system registers

Message ID 20191203225333.17055-11-richard.henderson@linaro.org
State New
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Series
  • target/arm: Implement ARMv8.1-PAN + ARMv8.2-ATS1E1
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Commit Message

Richard Henderson Dec. 3, 2019, 10:53 p.m.
This is a minor enhancement over ARMv8.1-PAN.
The *_PAN mmu_idx are used with the existing do_ats_write.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/helper.c | 50 +++++++++++++++++++++++++++++++++++++++------
 1 file changed, 44 insertions(+), 6 deletions(-)

-- 
2.17.1

Comments

Peter Maydell Dec. 9, 2019, 1:41 p.m. | #1
On Tue, 3 Dec 2019 at 22:53, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> This is a minor enhancement over ARMv8.1-PAN.

> The *_PAN mmu_idx are used with the existing do_ats_write.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/helper.c | 50 +++++++++++++++++++++++++++++++++++++++------

>  1 file changed, 44 insertions(+), 6 deletions(-)

>

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index 043e44d73d..f1eab4fb28 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -3360,16 +3360,20 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

>

>      switch (ri->opc2 & 6) {

>      case 0:

> -        /* stage 1 current state PL1: ATS1CPR, ATS1CPW */

> +        /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */

>          switch (el) {

>          case 3:

>              mmu_idx = ARMMMUIdx_SE3;

>              break;

>          case 2:

> -            mmu_idx = ARMMMUIdx_Stage1_E1;

> -            break;

> +            g_assert(!secure);  /* TODO: ARMv8.4-SecEL2 */

> +            /* fall through */

>          case 1:

> -            mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1;

> +            if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) {

> +                mmu_idx = secure ? ARMMMUIdx_SE1_PAN : ARMMMUIdx_Stage1_E1_PAN;

> +            } else {

> +                mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1;

> +            }


This way of writing it is fine, but just to check my understanding:
if the CPSR_PAN bit isn't set, then will a lookup via Idx_SE1_PAN
and a lookup via Idx_SE1 return the same results? (which would mean
you could drop the check on the PAN bit without changing behaviour).
Or do we guarantee that we only use the _PAN versions of the indexes
if the PAN bit is actually active?

> @@ -7426,6 +7434,36 @@ void register_cp_regs_for_features(ARMCPU *cpu)

>          };

>          define_arm_cp_regs(cpu, pan_reginfo);

>      }

> +#ifndef CONFIG_USER_ONLY

> +    if (cpu_isar_feature(aa64_ats1e1, cpu)) {

> +        static const ARMCPRegInfo ats1e1_reginfo[] = {

> +            { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,

> +              .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,

> +              .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,

> +              .writefn = ats_write64 },

> +            { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,

> +              .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,

> +              .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,

> +              .writefn = ats_write64 },

> +            REGINFO_SENTINEL

> +        };

> +        define_arm_cp_regs(cpu, ats1e1_reginfo);

> +    }

> +    if (cpu_isar_feature(aa32_ats1e1, cpu)) {

> +        static const ARMCPRegInfo ats1cp_reginfo[] = {

> +            { .name = "ATS1CPRP",

> +              .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,

> +              .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,

> +              .writefn = ats_write },

> +            { .name = "ATS1CPWP",

> +              .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,

> +              .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,

> +              .writefn = ats_write },

> +            REGINFO_SENTINEL

> +        };


I think having these at file scope rather than local is more
in line with the other regdefs.

> +        define_arm_cp_regs(cpu, ats1cp_reginfo);

> +    }

> +#endif


Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


thanks
-- PMM

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 043e44d73d..f1eab4fb28 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3360,16 +3360,20 @@  static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 
     switch (ri->opc2 & 6) {
     case 0:
-        /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
+        /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
         switch (el) {
         case 3:
             mmu_idx = ARMMMUIdx_SE3;
             break;
         case 2:
-            mmu_idx = ARMMMUIdx_Stage1_E1;
-            break;
+            g_assert(!secure);  /* TODO: ARMv8.4-SecEL2 */
+            /* fall through */
         case 1:
-            mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1;
+            if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) {
+                mmu_idx = secure ? ARMMMUIdx_SE1_PAN : ARMMMUIdx_Stage1_E1_PAN;
+            } else {
+                mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1;
+            }
             break;
         default:
             g_assert_not_reached();
@@ -3438,8 +3442,12 @@  static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
     switch (ri->opc2 & 6) {
     case 0:
         switch (ri->opc1) {
-        case 0: /* AT S1E1R, AT S1E1W */
-            mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1;
+        case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
+            if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) {
+                mmu_idx = secure ? ARMMMUIdx_SE1_PAN : ARMMMUIdx_Stage1_E1_PAN;
+            } else {
+                mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1;
+            }
             break;
         case 4: /* AT S1E2R, AT S1E2W */
             mmu_idx = ARMMMUIdx_E2;
@@ -7426,6 +7434,36 @@  void register_cp_regs_for_features(ARMCPU *cpu)
         };
         define_arm_cp_regs(cpu, pan_reginfo);
     }
+#ifndef CONFIG_USER_ONLY
+    if (cpu_isar_feature(aa64_ats1e1, cpu)) {
+        static const ARMCPRegInfo ats1e1_reginfo[] = {
+            { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
+              .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
+              .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+              .writefn = ats_write64 },
+            { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
+              .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
+              .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+              .writefn = ats_write64 },
+            REGINFO_SENTINEL
+        };
+        define_arm_cp_regs(cpu, ats1e1_reginfo);
+    }
+    if (cpu_isar_feature(aa32_ats1e1, cpu)) {
+        static const ARMCPRegInfo ats1cp_reginfo[] = {
+            { .name = "ATS1CPRP",
+              .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
+              .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+              .writefn = ats_write },
+            { .name = "ATS1CPWP",
+              .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
+              .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+              .writefn = ats_write },
+            REGINFO_SENTINEL
+        };
+        define_arm_cp_regs(cpu, ats1cp_reginfo);
+    }
+#endif
 
     if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
         static const ARMCPRegInfo vhe_reginfo[] = {