[4/4] target/arm: Enable ARMv8.2-UAO in -cpu max

Message ID 20191203234244.9124-5-richard.henderson@linaro.org
State Superseded
Headers show
Series
  • target/arm: Implement ARMv8.2-UAO
Related show

Commit Message

Richard Henderson Dec. 3, 2019, 11:42 p.m.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/cpu64.c | 4 ++++
 1 file changed, 4 insertions(+)

-- 
2.17.1

Comments

Peter Maydell Dec. 6, 2019, 6:31 p.m. | #1
On Tue, 3 Dec 2019 at 23:42, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/cpu64.c | 4 ++++

>  1 file changed, 4 insertions(+)

>

> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

> index 9399253b4c..03377084e3 100644

> --- a/target/arm/cpu64.c

> +++ b/target/arm/cpu64.c

> @@ -674,6 +674,10 @@ static void aarch64_max_initfn(Object *obj)

>          t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */

>          cpu->isar.id_aa64mmfr1 = t;

>

> +        t = cpu->isar.id_aa64mmfr2;

> +        t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);

> +        cpu->isar.id_aa64mmfr2 = t;

> +

>          /* Replicate the same data to the 32-bit id registers.  */

>          u = cpu->isar.id_isar5;

>          u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */

> --

> 2.17.1


Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


thanks
-- PMM

Patch

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 9399253b4c..03377084e3 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -674,6 +674,10 @@  static void aarch64_max_initfn(Object *obj)
         t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
         cpu->isar.id_aa64mmfr1 = t;
 
+        t = cpu->isar.id_aa64mmfr2;
+        t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
+        cpu->isar.id_aa64mmfr2 = t;
+
         /* Replicate the same data to the 32-bit id registers.  */
         u = cpu->isar.id_isar5;
         u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */