From patchwork Mon Dec 9 18:05:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 181083 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4693906ile; Mon, 9 Dec 2019 10:12:17 -0800 (PST) X-Google-Smtp-Source: APXvYqwvwykxTpN1OzXYSexrObWVY3rZuRuRtq9tWMkZtS3KfR9HvktDYnMP29u/1TlVNosSntTg X-Received: by 2002:a9d:768b:: with SMTP id j11mr22679229otl.116.1575915137102; Mon, 09 Dec 2019 10:12:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575915137; cv=none; d=google.com; s=arc-20160816; b=KrohNiW5faIUTfrYP9vEPJv8wpvH07PFka5STrhahIuwxFMZ/eM7hCSD4EcoigtiEY TluhGNTXU6ksubFvA5qbg8HdFV1AWlvaWg1WadTX27F+1E09azWLqDTGvw8nFqZH9Tk0 gscoERIdy2Q9vvs03jALqxce3444ZTkuR5/6yF2gFXcjBWUoeWWP4/sijq+u41m7D9wD Y/nZ3XOaXTBDpsmBHNB/OoDulDGIxMNJL/HZ+MYjPPwmwiw3Z6mnILLelf5a3nTW0mUu yiXK0Osn/uMowowBuIzV9J9+0yYBoT9ZN2RrWAZoPDFF9/iZq4ObDFLcoNWsFZFp1jnt UR4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/Jy95GpXuB41eeo4n20teyNgd1G2nU5TuzFz1RfMDZA=; b=apeA5u5VdWyjDSb8n93p9xmMPZPQIeWzLC/kAO7QNDHrhHCS5UIiRZYPCZozetAqkP 4pAvLR6toLxZHr6wCy6yfTVPCcahjMacwI4VoglJnwLlZumqRbt92aZU29pIPatD8gGL wri2ftAznLKf5yhG95cCF86aE1jdLRJybUF4lgYnhTJK2oAckdifZ7cCAw1DWm0Nkda/ 0J56EwysI/M0LCULbztMTlpr832IQvvoqmpn6ctJxX2YCK2aZmZiwKUoQE+1SizPTafG dDQ6Jl8AwU085IaDSoZ1FpAsFLNKylHCzwMaliHxW2aHNdqvLPgMrvEE8dhhZMA+pBrn G/Sg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MvHltTFk; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i8si333046oia.137.2019.12.09.10.12.16; Mon, 09 Dec 2019 10:12:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MvHltTFk; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726801AbfLISMQ (ORCPT + 8 others); Mon, 9 Dec 2019 13:12:16 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:51269 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726841AbfLISMM (ORCPT ); Mon, 9 Dec 2019 13:12:12 -0500 Received: by mail-wm1-f68.google.com with SMTP id g206so331725wme.1 for ; Mon, 09 Dec 2019 10:12:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/Jy95GpXuB41eeo4n20teyNgd1G2nU5TuzFz1RfMDZA=; b=MvHltTFkWGnrY2RUUt/dkF3Te3Whrbc5t+ayM4vXT51tU64XLFPJZeJU7Rli1Vf0Ax hqS2UxEW9ClFH/C9XrzEr2ISfSb2/DQPOTNtSg8rBwgnkIQrmd7o3zsY10EXytPjJW4p VQgHTBbnYhCCnZIG20X0WxqxtbVVbn8QwQwr7Kn+Mai3Ph0GzDMPahspuwZEBICeBzLp 56w+i2kRwO3y6jjuJm2+8rbFTC2GmVr5SlimgDOMcJeSYHprSnF8MBRjj2QRpqWzgO0f 0dN5Ceof6Xt2msBg9iqmuzRsGtLXZB26nHNoTNxMUJ6RT0YTPHabBPX4JyCNCGSaoLpA Yyvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/Jy95GpXuB41eeo4n20teyNgd1G2nU5TuzFz1RfMDZA=; b=HOBdQNEcusnzlzxAkmH9X3KTTxmh/QY//xVrXSmd36ZIg/BH9pssJvMpqYbBmY7OEE o0uGt4MwgqnmT3WmYKP2cBWz8s6dEwC5brx/38XpmvA4SD0SPXutcfaHyiY7NmBcomu9 IkBNVG3/Hrf1UMd8RoyMMgNJP3G2YdM+iBY8pW6RdP6QJuwvHWfZj8ACyvoZsVdTIM6Q 710h719K00ZmAbqOc5UeWVqrxnVLeE1pdok/qY0Ljgzaf5GC7tnkSJmKtxmbt2nCAAUv jKaox0HzVLyjRRSh2i9392YoKPEpSN7hfm0k3vwbOXrHetiuOsB9VwhVDlUgTCkyM2z9 GpCg== X-Gm-Message-State: APjAAAXWuM2a7JEC8wM3L/dHPlwY/x4Mx9k+h6MPMsH933Vj//yrvraD cacds5CKUrVdExcwg9/rBbvSpw== X-Received: by 2002:a05:600c:2c42:: with SMTP id r2mr393464wmg.8.1575915130505; Mon, 09 Dec 2019 10:12:10 -0800 (PST) Received: from localhost.localdomain (adsl-62-167-101-88.adslplus.ch. [62.167.101.88]) by smtp.gmail.com with ESMTPSA id h2sm309838wrv.66.2019.12.09.10.12.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2019 10:12:09 -0800 (PST) From: Jean-Philippe Brucker To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux-foundation.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, will@kernel.org, robin.murphy@arm.com, bhelgaas@google.com, eric.auger@redhat.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org Subject: [PATCH v3 13/13] iommu/arm-smmu-v3: Add support for PCI PASID Date: Mon, 9 Dec 2019 19:05:14 +0100 Message-Id: <20191209180514.272727-14-jean-philippe@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191209180514.272727-1-jean-philippe@linaro.org> References: <20191209180514.272727-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable PASID for PCI devices that support it. Since the SSID tables are allocated by arm_smmu_attach_dev(), PASID has to be enabled early enough. arm_smmu_dev_feature_enable() would be too late, since by that time the main DMA domain has already been attached. Do it in add_device() instead. Reviewed-by: Jonathan Cameron Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 51 ++++++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) -- 2.24.0 diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index d20a79108f8a..cde7af39681c 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -2643,6 +2643,49 @@ static void arm_smmu_disable_ats(struct arm_smmu_master *master) atomic_dec(&smmu_domain->nr_ats_masters); } +static int arm_smmu_enable_pasid(struct arm_smmu_master *master) +{ + int ret; + int features; + int num_pasids; + struct pci_dev *pdev; + + if (!dev_is_pci(master->dev)) + return -ENODEV; + + pdev = to_pci_dev(master->dev); + + features = pci_pasid_features(pdev); + if (features < 0) + return -ENODEV; + + num_pasids = pci_max_pasids(pdev); + if (num_pasids <= 0) + return -ENODEV; + + ret = pci_enable_pasid(pdev, features); + if (!ret) + master->ssid_bits = min_t(u8, ilog2(num_pasids), + master->smmu->ssid_bits); + return ret; +} + +static void arm_smmu_disable_pasid(struct arm_smmu_master *master) +{ + struct pci_dev *pdev; + + if (!dev_is_pci(master->dev)) + return; + + pdev = to_pci_dev(master->dev); + + if (!pdev->pasid_enabled) + return; + + master->ssid_bits = 0; + pci_disable_pasid(pdev); +} + static void arm_smmu_detach_dev(struct arm_smmu_master *master) { unsigned long flags; @@ -2851,13 +2894,16 @@ static int arm_smmu_add_device(struct device *dev) master->ssid_bits = min(smmu->ssid_bits, fwspec->num_pasid_bits); + /* Note that PASID must be enabled before, and disabled after ATS */ + arm_smmu_enable_pasid(master); + if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) master->ssid_bits = min_t(u8, master->ssid_bits, CTXDESC_LINEAR_CDMAX); ret = iommu_device_link(&smmu->iommu, dev); if (ret) - goto err_free_master; + goto err_disable_pasid; group = iommu_group_get_for_dev(dev); if (IS_ERR(group)) { @@ -2870,6 +2916,8 @@ static int arm_smmu_add_device(struct device *dev) err_unlink: iommu_device_unlink(&smmu->iommu, dev); +err_disable_pasid: + arm_smmu_disable_pasid(master); err_free_master: kfree(master); fwspec->iommu_priv = NULL; @@ -2890,6 +2938,7 @@ static void arm_smmu_remove_device(struct device *dev) arm_smmu_detach_dev(master); iommu_group_remove_device(dev); iommu_device_unlink(&smmu->iommu, dev); + arm_smmu_disable_pasid(master); kfree(master); iommu_fwspec_free(dev); }