From patchwork Fri Dec 20 10:17:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 182229 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp325804ilf; Fri, 20 Dec 2019 02:17:50 -0800 (PST) X-Google-Smtp-Source: APXvYqygI30vZI2NRdym1PNRVnMb8MQH6+ZHBCtimj0sa6Pe9slevKR6riTY0H7GeBSnUBH0MFaG X-Received: by 2002:a9d:5616:: with SMTP id e22mr13692526oti.366.1576837070469; Fri, 20 Dec 2019 02:17:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576837070; cv=none; d=google.com; s=arc-20160816; b=TCkAM88UNbrWSGS29e/JvxCP/f7i1ZQ6A07YGiWeH3Bc8vOHQopMpcyapflEoP5e6W /++GOPjCLA2Hxtw3brkshsYAGICyGc8rPSuW89EPDipqu1jXDD9duw7hORVn8EHE5Heg MKmDx7ktp4SBfOpcbSFo4/y+BSpE/FxK6pdxHt9RW+emYdDaVVINxLve6wADo1DHvGYx 3VO4gEa0jj2Q8AEk9GxL9DYxXPamdqBiLbHdFApk3x1VDwFsHn9x2T8QWoI84yZ6fZYb bAg6Igo0iV4KmaouwO72cdb7jPRTSMyNC9XWLtaUcoDFXfT7aMTd/clRXAMWBjxSFuLW BjVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ySyIYzqBpCfWbUlWOn49FAmGg4GlPY2orfOBkmTiBXk=; b=z6O0O+DeQVdzPFf1RVXMzCjohMeQSJ6/gzyVzRUJKK7uIRf8BlKomfPpETZjn36aYY MfgJ9bLghUIx0DDjChZNhu9UnUZ0RFwQibgJhw1kK1BGW0EP5z3MnRJBqAZCLY17UT2d zmRv6aUF42ht9V4Pcomv/MKFAxLW3IIbT/ozT493+N061MhoJRoZSwJEABX4T6ZrqAAm wASz9uMRo0/HgS/SujlXz7d5kyg7jhcSb5Ns+Euz0Qar7f/4CFMX7ERhqgRfcEY/lkzE ONPXLZnyVElmQp52MMDgIqHAul4kyT+QGN05NLh6TTVpMGJd4FSdOD+fXfNnf3ZFwMNI 4sSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=Pek5gpwX; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d6si5116826otq.41.2019.12.20.02.17.50; Fri, 20 Dec 2019 02:17:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=Pek5gpwX; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727276AbfLTKRt (ORCPT + 15 others); Fri, 20 Dec 2019 05:17:49 -0500 Received: from mail.kernel.org ([198.145.29.99]:53184 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727327AbfLTKRt (ORCPT ); Fri, 20 Dec 2019 05:17:49 -0500 Received: from localhost.localdomain (unknown [106.201.107.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id AC00F24685; Fri, 20 Dec 2019 10:17:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1576837068; bh=9y+vE6be/fQg89xEmZaoRg10l2d1ad2HMwJK38tcPPo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Pek5gpwXHKbqG0cPWLKoN1eHZXptlJROT1u799eqAhU4dZ5tI1/IKP2caoTQHk2b4 nEG/JO1B2/yVpEub4V/AnObpUSzvwqMjIQZDuERG9q+WxHIWCEqGwGislHMT43+NVx iKtMWxDgRTJwtqr8k70e6DXf3K8T/rRJi2qz4ZGc= From: Vinod Koul To: Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Can Guo , Jeffrey Hugo , linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] phy: qcom-qmp: Add optional SW reset Date: Fri, 20 Dec 2019 15:47:17 +0530 Message-Id: <20191220101719.3024693-4-vkoul@kernel.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191220101719.3024693-1-vkoul@kernel.org> References: <20191220101719.3024693-1-vkoul@kernel.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and then deassert it, so add optional has_sw_reset flag and use that to configure the QPHY_SW_RESET register. Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.23.0 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 1196c85aa023..47a66d55107d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -168,6 +168,7 @@ static const unsigned int sdm845_ufsphy_regs_layout[] = { static const unsigned int sm8150_ufsphy_regs_layout[] = { [QPHY_START_CTRL] = QPHY_V4_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_READY_STATUS, + [QPHY_SW_RESET] = QPHY_V4_SW_RESET, }; static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { @@ -1023,6 +1024,9 @@ struct qmp_phy_cfg { /* true, if PCS block has no separate SW_RESET register */ bool no_pcs_sw_reset; + + /* true if sw reset needs to be invoked */ + bool has_sw_reset; }; /** @@ -1391,6 +1395,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .is_dual_lane_phy = true, .no_pcs_sw_reset = true, + .has_sw_reset = true, }; static void qcom_qmp_phy_configure(void __iomem *base, @@ -1475,6 +1480,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); } + if (cfg->has_sw_reset) + qphy_setbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + if (cfg->has_phy_com_ctrl) qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], SW_PWRDN); @@ -1651,6 +1659,9 @@ static int qcom_qmp_phy_enable(struct phy *phy) if (cfg->has_phy_dp_com_ctrl) qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); + if (cfg->has_sw_reset) + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);