From patchwork Fri Dec 20 15:05:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 182303 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp647438ilf; Fri, 20 Dec 2019 07:06:03 -0800 (PST) X-Google-Smtp-Source: APXvYqwqBjICRDCwMvLAjfKj/xtlSMtYihzkHLXf22wfx0L5fWRgakx0O+65camoAKkIKxWjboXK X-Received: by 2002:a05:6830:593:: with SMTP id c19mr12000607oth.224.1576854363616; Fri, 20 Dec 2019 07:06:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576854363; cv=none; d=google.com; s=arc-20160816; b=H5/EnbEIpXvSQNDPu0FVnUYThdFa6QAIvEB2gTNQvA8bLFs1XVw18/ZGVQ7Bk4DBI1 pmx23I5TF4IdYhS73dq8n83zKduo8sZOmD94ltGDEPg0fUgz+fdfhpfDug/QMis+w7uk 02FGAKDwNzgtDiPTX/r+8eYLwd7vJ65UOFo3pKfpuhwxEAm3+LfrD1ZEPsWsLGPx6YPQ USnSJf/Kxh3B7ebCvZ2DmAlPbpOSy8ydrY8yni1++/iC1c6lNTyJm9Z7VMIiuyK3RSjZ fT3wiEHdkqR7FOqINxc3Fsg45+ZaJmdEvYUrnwZyDXw6JwNoNWBjnjRnL0bAFcbpBKUS mb9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=zqubgS86nr3bz5n0De08HJPcvX3pIiv/Tclr9jElceM=; b=IGfxka4Qs4VxzhZzf/XbRUwLxal/sZFgqQHx9gUbXo3ZZp66FFcBMAqiWmWRzKPNZa WO9ftycFFcAQkvztptdWW2PwtZMgPH7hM0un8SEyoqHoYdujpvHTWGl9LXPOUwFTSQ/8 cgAKUPT0vZhsyzXRr7vurv8vhW+0tcYbKQu5oHfs0GaK5cqz2sGwyDrQ7v1xOprZjyYA TFo4nypXeyhmX9Nm/QYaH33eOzBN5qduASOMYrBJ1XArR+wH4ncrYE0ty731b12UW2Qs 4uPNKJmGPeNxTCR24RY9hhQoAKwqCx2ew+ktpkWM4RBr4HY4xjRpdSE5O4rDdla+Qkdg iAhA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c2si2779188oig.255.2019.12.20.07.06.03; Fri, 20 Dec 2019 07:06:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727391AbfLTPGD (ORCPT + 14 others); Fri, 20 Dec 2019 10:06:03 -0500 Received: from foss.arm.com ([217.140.110.172]:52226 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727233AbfLTPGC (ORCPT ); Fri, 20 Dec 2019 10:06:02 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4AEEF31B; Fri, 20 Dec 2019 07:06:02 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BB7753F6CF; Fri, 20 Dec 2019 07:06:00 -0800 (PST) From: Mark Rutland To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Mark Rutland , Alexandru Elisei , Drew Jones , James Morse , Julien Thierry , Peter Maydell , Suzuki K Poulose , Will Deacon , stable@vger.kernel.org Subject: [PATCH 3/3] KVM: arm/arm64: correct AArch32 SPSR on exception entry Date: Fri, 20 Dec 2019 15:05:49 +0000 Message-Id: <20191220150549.31948-4-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191220150549.31948-1-mark.rutland@arm.com> References: <20191220150549.31948-1-mark.rutland@arm.com> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Confusingly, there are three SPSR layouts that a kernel may need to deal with: (1) An AArch64 SPSR_ELx view of an AArch64 pstate (2) An AArch64 SPSR_ELx view of an AArch32 pstate (3) An AArch32 SPSR_* view of an AArch32 pstate When the KVM AArch32 support code deals with SPSR_{EL2,HYP}, it's either dealing with #2 or #3 consistently. On arm64 the PSR_AA32_* definitions match the AArch64 SPSR_ELx view, and on arm the PSR_AA32_* definitions match the AArch32 SPSR_* view. However, when we inject an exception into an AArch32 guest, we have to synthesize the AArch32 SPSR_* that the guest will see. Thus, an AArch64 host needs to synthesize layout #3 from layout #2. This patch adds a new host_spsr_to_spsr32() helper for this, and makes use of it in the KVM AArch32 support code. For arm64 we need to shuffle the DIT bit around, and remove the SS bit, while for arm we can use the value as-is. I've open-coded the bit manipulation for now to avoid having to rework the existing PSR_* definitions into PSR64_AA32_* and PSR32_AA32_* definitions. I hope to perform a more thorough refactoring in future so that we can handle pstate view manipulation more consistently across the kernel tree. Signed-off-by: Mark Rutland Cc: Alexandru Elisei Cc: Drew Jones Cc: James Morse Cc: Julien Thierry Cc: Marc Zyngier Cc: Peter Maydell Cc: Suzuki K Poulose Cc: Will Deacon Cc: stable@vger.kernel.org --- arch/arm/include/asm/kvm_emulate.h | 5 +++++ arch/arm64/include/asm/kvm_emulate.h | 32 ++++++++++++++++++++++++++++++++ virt/kvm/arm/aarch32.c | 6 +++--- 3 files changed, 40 insertions(+), 3 deletions(-) -- 2.11.0 Reviewed-by: Alexandru Elisei diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h index dee2567661ed..b811576bc456 100644 --- a/arch/arm/include/asm/kvm_emulate.h +++ b/arch/arm/include/asm/kvm_emulate.h @@ -53,6 +53,11 @@ static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v) *__vcpu_spsr(vcpu) = v; } +static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) +{ + return spsr; +} + static inline unsigned long vcpu_get_reg(struct kvm_vcpu *vcpu, u8 reg_num) { diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index d69c1efc63e7..98672938f9f9 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -204,6 +204,38 @@ static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v) vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v; } +/* + * The layout of SPSR for an AArch32 state is different when observed from an + * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32 + * view given an AArch64 view. + * + * In ARM DDI 0487E.a see: + * + * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426 + * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256 + * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280 + * + * Which show the following differences: + * + * | Bit | AA64 | AA32 | Notes | + * +-----+------+------+-----------------------------| + * | 24 | DIT | J | J is RES0 in ARMv8 | + * | 21 | SS | DIT | SS doesn't exist in AArch32 | + * + * ... and all other bits are (currently) common. + */ +static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) +{ + const unsigned long overlap = BIT(24) | BIT(21); + unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT); + + spsr &= overlap; + + spsr |= dit << 21; + + return spsr; +} + static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) { u32 mode; diff --git a/virt/kvm/arm/aarch32.c b/virt/kvm/arm/aarch32.c index 17bcde5c2451..115210e64682 100644 --- a/virt/kvm/arm/aarch32.c +++ b/virt/kvm/arm/aarch32.c @@ -128,15 +128,15 @@ static unsigned long get_except32_cpsr(struct kvm_vcpu *vcpu, u32 mode) static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset) { - unsigned long new_spsr_value = *vcpu_cpsr(vcpu); - bool is_thumb = (new_spsr_value & PSR_AA32_T_BIT); + unsigned long spsr = *vcpu_cpsr(vcpu); + bool is_thumb = (spsr & PSR_AA32_T_BIT); u32 return_offset = return_offsets[vect_offset >> 2][is_thumb]; u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR); *vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode); /* Note: These now point to the banked copies */ - vcpu_write_spsr(vcpu, new_spsr_value); + vcpu_write_spsr(vcpu, host_spsr_to_spsr32(spsr)); *vcpu_reg32(vcpu, 14) = *vcpu_pc(vcpu) + return_offset; /* Branch to exception vector */