| Message ID | 20200127123934.11847-1-yamada.masahiro@socionext.com |
|---|---|
| State | New |
| Headers | show |
| Series | mtd: rawnand: denali: deassert write protect pin | expand |
On Mon, 2020-01-27 at 12:39:34 UTC, Masahiro Yamada wrote: > If the write protect signal from this IP is connected to the NAND > device, this IP can handle the WP# pin via the WRITE_PROTECT > register. > > The Denali NAND Flash Memory Controller User's Guide describes > this register like follows: > > When the controller is in reset, the WP# pin is always asserted > to the device. Once the reset is removed, the WP# is de-asserted. > The software will then have to come and program this bit to > assert/de-assert the same. > > 1 - Write protect de-assert > 0 - Write protect assert > > The default value is 1, so the write protect is de-asserted after > the reset is removed. The driver can write to the device unless > someone has explicitly cleared register before booting the kernel. > > The boot ROM of some UniPhier SoCs (LD4, Pro4, sLD8, Pro5) is the > case; the boot ROM clears the WRITE_PROTECT register when the system > is booting from the NAND device, so the NAND device becomes read-only. > > Set it to 1 in the driver in order to allow the write access to the > device. > > Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks. Miquel ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index fafd0a0aa8e2..6a6c919b2569 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -1317,6 +1317,7 @@ int denali_init(struct denali_controller *denali) iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); iowrite32(ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE); iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); + iowrite32(WRITE_PROTECT__FLAG, denali->reg + WRITE_PROTECT); denali_clear_irq_all(denali);
If the write protect signal from this IP is connected to the NAND device, this IP can handle the WP# pin via the WRITE_PROTECT register. The Denali NAND Flash Memory Controller User's Guide describes this register like follows: When the controller is in reset, the WP# pin is always asserted to the device. Once the reset is removed, the WP# is de-asserted. The software will then have to come and program this bit to assert/de-assert the same. 1 - Write protect de-assert 0 - Write protect assert The default value is 1, so the write protect is de-asserted after the reset is removed. The driver can write to the device unless someone has explicitly cleared register before booting the kernel. The boot ROM of some UniPhier SoCs (LD4, Pro4, sLD8, Pro5) is the case; the boot ROM clears the WRITE_PROTECT register when the system is booting from the NAND device, so the NAND device becomes read-only. Set it to 1 in the driver in order to allow the write access to the device. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> --- drivers/mtd/nand/raw/denali.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/