From patchwork Mon Feb 10 19:20:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 183258 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp4418020ile; Mon, 10 Feb 2020 11:22:34 -0800 (PST) X-Google-Smtp-Source: APXvYqyuQtEcRjMhOefum/G+84DYQD9cMfDWJARy/BfBTj71fqKCIq3lLrI1P6gB00EmjASOlDzh X-Received: by 2002:aca:4e02:: with SMTP id c2mr408276oib.142.1581362554256; Mon, 10 Feb 2020 11:22:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581362554; cv=none; d=google.com; s=arc-20160816; b=dm4q+DoeleVpXqH8n+R/2B1tA2S2m441qmLtZ3VPtmBxpNn22fTfIG5JmV8kaFA8K0 VnJ/U+pDsHXDmZLQ66HVXxwNBbDn2+LUQrcBYeCQxrYaSuEWQcy341/WpvpaZKSh/fcW YlubhXQaAF+DPYDYUIqawEBXPWSUdanq+YLEOhqAru9DmK/4ZgS3uof1D+RMoGZ1Behn emsv3hbRvwlNGdMSxHKg8LslCuPc43VGLVXB9VhFzhgiLAZ0Y8CX5an3Lbei14XNK+5v neealxfb1wsyCaUeXm2quaLdo4DYDGPLS5/k2XaSTasAl32xWdKRfHubBdk8VZ5AFm6O hcrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:delivered-to:sender:list-help:list-post:list-archive :list-subscribe:list-unsubscribe:list-id:precedence:mailing-list :dkim-signature:domainkey-signature; bh=XeP7B2e8mE4eHzQ3fGu7Yta/QYF+X0JL2lrZPqqc2PU=; b=KryMlcxDXscxgpbCTrdj57eWtJEsBV9iT5fpxfv6kLLeEAMhXlV9cGkXUkGW7Jpthe ErmVT7OI5WuftAGQ5mLiwM39F1AUxLxQMQpTcgxTySkyWAuhntvaX2A3UZGI+wHE+fPa BKa1NIV6V0TUuqXxXO+GohAYQVAJFciOvRBcZar1IOBwqyCNW7q81dgWsFM9D4MFRBnk o26mORTKCa/K540E4fgRlDqrzPERuW2xfB0oFRBkMh6sq8/NI3BLxGLLh54hU2AHmUfJ 5Q3WWsTLLN4Yno+nUNPA3QUWA3LVNUx46YmHZiLZOH6FO3Zw8dFrtYchmltSqajbxWY3 ygLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=GIZF1XEo; dkim=pass header.i=@linaro.org header.s=google header.b=DffbpFjD; spf=pass (google.com: domain of libc-alpha-return-109395-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="libc-alpha-return-109395-patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id s26si600817otp.172.2020.02.10.11.22.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Feb 2020 11:22:34 -0800 (PST) Received-SPF: pass (google.com: domain of libc-alpha-return-109395-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=GIZF1XEo; dkim=pass header.i=@linaro.org header.s=google header.b=DffbpFjD; spf=pass (google.com: domain of libc-alpha-return-109395-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="libc-alpha-return-109395-patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=YvWIOyzUi//jPTzqYslaR25w04nobep vTXX+982Vv1VB0GPFRzsTjFpRapplclYicoHtEGV+RgwW/Dl61msGpuSLf+Mi4Xk /mgBb67drDYDBkIyIhdqIRhTFJheZMYvJvy4WjQZ5AjxFNH9NSvyjz8cS/3Y7Zl/ ze/KR8rlZfD0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; s=default; bh=nN1LUs8uWf8v56RmsnaQ1qouwmk=; b=GIZF1 XEokiAm/3IaT3biIICnzI3tZw5Yb0tJEynz2kBQXgK/aaiHVTuyGa2Qmzaz4qZpV fDhH0cQnExOpPbFGoxNz9tceCsLuS6+AbgUg67pN+jVrvKauCRahbl9y/GeQ30Yn Z9XCMbzhb5FUSvRVPcPHkz1/hQKHzyUlcNPhKs= Received: (qmail 100591 invoked by alias); 10 Feb 2020 19:20:59 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 100525 invoked by uid 89); 10 Feb 2020 19:20:58 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-22.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-qv1-f66.google.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=XeP7B2e8mE4eHzQ3fGu7Yta/QYF+X0JL2lrZPqqc2PU=; b=DffbpFjDNt2Xfwh+EcoPO9R3+fdDKwvhZS03Ev+144TUur+iHkA95edpAA36rT/pjY pMctxDP8oo28MqvDWbTKUloqVvkkN3Qru43XZjNDCix1ccQeV7IU+RKGd39tZl9erNho Qe5qpBT+vcDzBeyxOFje5xMiSj1xb73CXVsSZZ4tQ7SjpG//y64fsP98prlbbEx+CGE6 C24IqGcPdAaF9Ojjigfsu/1d6Ik/D82ZMR+w8rF5UXI6mBJxgqIobIfkEgMY5EpUDsWh rBTL7cLdTYEErqkQXwyQBzwhIXkRBtOz0RYiYpzarLDvn2UepCNZ9ar31xQCNP+3KyMl bIaw== Return-Path: From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH 10/15] riscv: Avoid clobbering register parameters in syscall Date: Mon, 10 Feb 2020 16:20:33 -0300 Message-Id: <20200210192038.23588-10-adhemerval.zanella@linaro.org> In-Reply-To: <20200210192038.23588-1-adhemerval.zanella@linaro.org> References: <20200210192038.23588-1-adhemerval.zanella@linaro.org> The riscv INTERNAL_SYSCALL macro might clobber the register parameter if the argument itself might clobber any register (a function call for instance). This patch fixes it by using temporary variables for the expressions between the register assignments (as indicated by GCC documentation, 6.47.5.2 Specifying Registers for Local Variables). It is similar to the fix done for MIPS (BZ#25523). Checked with riscv64-linux-gnu-rv64imafdc-lp64d build. --- sysdeps/unix/sysv/linux/riscv/sysdep.h | 84 +++++++++++++++++--------- 1 file changed, 56 insertions(+), 28 deletions(-) -- 2.17.1 diff --git a/sysdeps/unix/sysv/linux/riscv/sysdep.h b/sysdeps/unix/sysv/linux/riscv/sysdep.h index 201bf9a91b..2bd9b16f32 100644 --- a/sysdeps/unix/sysv/linux/riscv/sysdep.h +++ b/sysdeps/unix/sysv/linux/riscv/sysdep.h @@ -176,10 +176,11 @@ # define internal_syscall1(number, err, arg0) \ ({ \ long int _sys_result; \ + long int _arg0 = (long int) (arg0); \ \ { \ register long int __a7 asm ("a7") = number; \ - register long int __a0 asm ("a0") = (long int) (arg0); \ + register long int __a0 asm ("a0") = _arg0; \ __asm__ volatile ( \ "scall\n\t" \ : "+r" (__a0) \ @@ -193,11 +194,13 @@ # define internal_syscall2(number, err, arg0, arg1) \ ({ \ long int _sys_result; \ + long int _arg0 = (long int) (arg0); \ + long int _arg1 = (long int) (arg1); \ \ { \ register long int __a7 asm ("a7") = number; \ - register long int __a0 asm ("a0") = (long int) (arg0); \ - register long int __a1 asm ("a1") = (long int) (arg1); \ + register long int __a0 asm ("a0") = _arg0; \ + register long int __a1 asm ("a1") = _arg1; \ __asm__ volatile ( \ "scall\n\t" \ : "+r" (__a0) \ @@ -211,12 +214,15 @@ # define internal_syscall3(number, err, arg0, arg1, arg2) \ ({ \ long int _sys_result; \ + long int _arg0 = (long int) (arg0); \ + long int _arg1 = (long int) (arg1); \ + long int _arg2 = (long int) (arg2); \ \ { \ register long int __a7 asm ("a7") = number; \ - register long int __a0 asm ("a0") = (long int) (arg0); \ - register long int __a1 asm ("a1") = (long int) (arg1); \ - register long int __a2 asm ("a2") = (long int) (arg2); \ + register long int __a0 asm ("a0") = _arg0; \ + register long int __a1 asm ("a1") = _arg1; \ + register long int __a2 asm ("a2") = _arg2; \ __asm__ volatile ( \ "scall\n\t" \ : "+r" (__a0) \ @@ -230,13 +236,17 @@ # define internal_syscall4(number, err, arg0, arg1, arg2, arg3) \ ({ \ long int _sys_result; \ + long int _arg0 = (long int) (arg0); \ + long int _arg1 = (long int) (arg1); \ + long int _arg2 = (long int) (arg2); \ + long int _arg3 = (long int) (arg3); \ \ { \ register long int __a7 asm ("a7") = number; \ - register long int __a0 asm ("a0") = (long int) (arg0); \ - register long int __a1 asm ("a1") = (long int) (arg1); \ - register long int __a2 asm ("a2") = (long int) (arg2); \ - register long int __a3 asm ("a3") = (long int) (arg3); \ + register long int __a0 asm ("a0") = _arg0; \ + register long int __a1 asm ("a1") = _arg1; \ + register long int __a2 asm ("a2") = _arg2; \ + register long int __a3 asm ("a3") = _arg3; \ __asm__ volatile ( \ "scall\n\t" \ : "+r" (__a0) \ @@ -250,14 +260,19 @@ # define internal_syscall5(number, err, arg0, arg1, arg2, arg3, arg4) \ ({ \ long int _sys_result; \ + long int _arg0 = (long int) (arg0); \ + long int _arg1 = (long int) (arg1); \ + long int _arg2 = (long int) (arg2); \ + long int _arg3 = (long int) (arg3); \ + long int _arg4 = (long int) (arg4); \ \ { \ register long int __a7 asm ("a7") = number; \ - register long int __a0 asm ("a0") = (long int) (arg0); \ - register long int __a1 asm ("a1") = (long int) (arg1); \ - register long int __a2 asm ("a2") = (long int) (arg2); \ - register long int __a3 asm ("a3") = (long int) (arg3); \ - register long int __a4 asm ("a4") = (long int) (arg4); \ + register long int __a0 asm ("a0") = _arg0; \ + register long int __a1 asm ("a1") = _arg1; \ + register long int __a2 asm ("a2") = _arg2; \ + register long int __a3 asm ("a3") = _arg3; \ + register long int __a4 asm ("a4") = _arg4; \ __asm__ volatile ( \ "scall\n\t" \ : "+r" (__a0) \ @@ -271,15 +286,21 @@ # define internal_syscall6(number, err, arg0, arg1, arg2, arg3, arg4, arg5) \ ({ \ long int _sys_result; \ + long int _arg0 = (long int) (arg0); \ + long int _arg1 = (long int) (arg1); \ + long int _arg2 = (long int) (arg2); \ + long int _arg3 = (long int) (arg3); \ + long int _arg4 = (long int) (arg4); \ + long int _arg5 = (long int) (arg5); \ \ { \ register long int __a7 asm ("a7") = number; \ - register long int __a0 asm ("a0") = (long int) (arg0); \ - register long int __a1 asm ("a1") = (long int) (arg1); \ - register long int __a2 asm ("a2") = (long int) (arg2); \ - register long int __a3 asm ("a3") = (long int) (arg3); \ - register long int __a4 asm ("a4") = (long int) (arg4); \ - register long int __a5 asm ("a5") = (long int) (arg5); \ + register long int __a0 asm ("a0") = _arg0; \ + register long int __a1 asm ("a1") = _arg1; \ + register long int __a2 asm ("a2") = _arg2; \ + register long int __a3 asm ("a3") = _arg3; \ + register long int __a4 asm ("a4") = _arg4; \ + register long int __a5 asm ("a5") = _arg5; \ __asm__ volatile ( \ "scall\n\t" \ : "+r" (__a0) \ @@ -294,16 +315,23 @@ # define internal_syscall7(number, err, arg0, arg1, arg2, arg3, arg4, arg5, arg6) \ ({ \ long int _sys_result; \ + long int _arg0 = (long int) (arg0); \ + long int _arg1 = (long int) (arg1); \ + long int _arg2 = (long int) (arg2); \ + long int _arg3 = (long int) (arg3); \ + long int _arg4 = (long int) (arg4); \ + long int _arg5 = (long int) (arg5); \ + long int _arg6 = (long int) (arg6); \ \ { \ register long int __a7 asm ("a7") = number; \ - register long int __a0 asm ("a0") = (long int) (arg0); \ - register long int __a1 asm ("a1") = (long int) (arg1); \ - register long int __a2 asm ("a2") = (long int) (arg2); \ - register long int __a3 asm ("a3") = (long int) (arg3); \ - register long int __a4 asm ("a4") = (long int) (arg4); \ - register long int __a5 asm ("a5") = (long int) (arg5); \ - register long int __a6 asm ("a6") = (long int) (arg6); \ + register long int __a0 asm ("a0") = _arg0; \ + register long int __a1 asm ("a1") = _arg1; \ + register long int __a2 asm ("a2") = _arg2; \ + register long int __a3 asm ("a3") = _arg3; \ + register long int __a4 asm ("a4") = _arg4; \ + register long int __a5 asm ("a5") = _arg5; \ + register long int __a6 asm ("a6") = _arg6; \ __asm__ volatile ( \ "scall\n\t" \ : "+r" (__a0) \