diff mbox series

[04/13] target/arm: Factor out PMU register definitions

Message ID 20200211173726.22541-5-peter.maydell@linaro.org
State Superseded
Headers show
Series arm: Implement ARMv8.1-PMU and ARMv8.4-PMU | expand

Commit Message

Peter Maydell Feb. 11, 2020, 5:37 p.m. UTC 
Pull the code that defines the various PMU registers out
into its own function, matching the pattern we have
already for the debug registers.

Apart from one style fix to a multi-line comment, this
is purely movement of code with no changes to it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/helper.c | 158 +++++++++++++++++++++++---------------------
 1 file changed, 82 insertions(+), 76 deletions(-)

-- 
2.20.1

Comments

Richard Henderson Feb. 11, 2020, 6:30 p.m. UTC | #1 
On 2/11/20 9:37 AM, Peter Maydell wrote:
> Pull the code that defines the various PMU registers out

> into its own function, matching the pattern we have

> already for the debug registers.

> 

> Apart from one style fix to a multi-line comment, this

> is purely movement of code with no changes to it.

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>  target/arm/helper.c | 158 +++++++++++++++++++++++---------------------

>  1 file changed, 82 insertions(+), 76 deletions(-)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>



r~
Philippe Mathieu-Daudé Feb. 12, 2020, 6:40 a.m. UTC | #2 
On 2/11/20 6:37 PM, Peter Maydell wrote:
> Pull the code that defines the various PMU registers out

> into its own function, matching the pattern we have

> already for the debug registers.

> 

> Apart from one style fix to a multi-line comment, this

> is purely movement of code with no changes to it.

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>   target/arm/helper.c | 158 +++++++++++++++++++++++---------------------

>   1 file changed, 82 insertions(+), 76 deletions(-)

> 

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index bf083c369fc..0011a22f42d 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -5822,6 +5822,87 @@ static void define_debug_regs(ARMCPU *cpu)

>       }

>   }

>   

> +static void define_pmu_regs(ARMCPU *cpu)

> +{

> +    /*

> +     * v7 performance monitor control register: same implementor

> +     * field as main ID register, and we implement four counters in

> +     * addition to the cycle count register.

> +     */

> +    unsigned int i, pmcrn = 4;

> +    ARMCPRegInfo pmcr = {

> +        .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,

> +        .access = PL0_RW,

> +        .type = ARM_CP_IO | ARM_CP_ALIAS,

> +        .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),

> +        .accessfn = pmreg_access, .writefn = pmcr_write,

> +        .raw_writefn = raw_write,

> +    };

> +    ARMCPRegInfo pmcr64 = {

> +        .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,

> +        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,

> +        .access = PL0_RW, .accessfn = pmreg_access,

> +        .type = ARM_CP_IO,

> +        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),

> +        .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),

> +        .writefn = pmcr_write, .raw_writefn = raw_write,

> +    };

> +    define_one_arm_cp_reg(cpu, &pmcr);

> +    define_one_arm_cp_reg(cpu, &pmcr64);

> +    for (i = 0; i < pmcrn; i++) {

> +        char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);

> +        char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);

> +        char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);

> +        char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);

> +        ARMCPRegInfo pmev_regs[] = {

> +            { .name = pmevcntr_name, .cp = 15, .crn = 14,

> +              .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,

> +              .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,

> +              .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,

> +              .accessfn = pmreg_access },

> +            { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,

> +              .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),

> +              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,

> +              .type = ARM_CP_IO,

> +              .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,

> +              .raw_readfn = pmevcntr_rawread,

> +              .raw_writefn = pmevcntr_rawwrite },

> +            { .name = pmevtyper_name, .cp = 15, .crn = 14,

> +              .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,

> +              .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,

> +              .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,

> +              .accessfn = pmreg_access },

> +            { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,

> +              .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),

> +              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,

> +              .type = ARM_CP_IO,

> +              .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,

> +              .raw_writefn = pmevtyper_rawwrite },

> +            REGINFO_SENTINEL

> +        };

> +        define_arm_cp_regs(cpu, pmev_regs);

> +        g_free(pmevcntr_name);

> +        g_free(pmevcntr_el0_name);

> +        g_free(pmevtyper_name);

> +        g_free(pmevtyper_el0_name);

> +    }

> +    if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&

> +            FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {

> +        ARMCPRegInfo v81_pmu_regs[] = {

> +            { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,

> +              .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,

> +              .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,

> +              .resetvalue = extract64(cpu->pmceid0, 32, 32) },

> +            { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,

> +              .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,

> +              .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,

> +              .resetvalue = extract64(cpu->pmceid1, 32, 32) },

> +            REGINFO_SENTINEL

> +        };

> +        define_arm_cp_regs(cpu, v81_pmu_regs);

> +    }

> +}

> +

>   /* We don't know until after realize whether there's a GICv3

>    * attached, and that is what registers the gicv3 sysregs.

>    * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1

> @@ -6244,67 +6325,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)

>           define_arm_cp_regs(cpu, pmovsset_cp_reginfo);

>       }

>       if (arm_feature(env, ARM_FEATURE_V7)) {

> -        /* v7 performance monitor control register: same implementor

> -         * field as main ID register, and we implement four counters in

> -         * addition to the cycle count register.

> -         */

> -        unsigned int i, pmcrn = 4;

> -        ARMCPRegInfo pmcr = {

> -            .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,

> -            .access = PL0_RW,

> -            .type = ARM_CP_IO | ARM_CP_ALIAS,

> -            .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),

> -            .accessfn = pmreg_access, .writefn = pmcr_write,

> -            .raw_writefn = raw_write,

> -        };

> -        ARMCPRegInfo pmcr64 = {

> -            .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,

> -            .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,

> -            .access = PL0_RW, .accessfn = pmreg_access,

> -            .type = ARM_CP_IO,

> -            .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),

> -            .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),

> -            .writefn = pmcr_write, .raw_writefn = raw_write,

> -        };

> -        define_one_arm_cp_reg(cpu, &pmcr);

> -        define_one_arm_cp_reg(cpu, &pmcr64);

> -        for (i = 0; i < pmcrn; i++) {

> -            char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);

> -            char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);

> -            char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);

> -            char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);

> -            ARMCPRegInfo pmev_regs[] = {

> -                { .name = pmevcntr_name, .cp = 15, .crn = 14,

> -                  .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,

> -                  .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,

> -                  .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,

> -                  .accessfn = pmreg_access },

> -                { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,

> -                  .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),

> -                  .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,

> -                  .type = ARM_CP_IO,

> -                  .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,

> -                  .raw_readfn = pmevcntr_rawread,

> -                  .raw_writefn = pmevcntr_rawwrite },

> -                { .name = pmevtyper_name, .cp = 15, .crn = 14,

> -                  .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,

> -                  .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,

> -                  .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,

> -                  .accessfn = pmreg_access },

> -                { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,

> -                  .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),

> -                  .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,

> -                  .type = ARM_CP_IO,

> -                  .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,

> -                  .raw_writefn = pmevtyper_rawwrite },

> -                REGINFO_SENTINEL

> -            };

> -            define_arm_cp_regs(cpu, pmev_regs);

> -            g_free(pmevcntr_name);

> -            g_free(pmevcntr_el0_name);

> -            g_free(pmevtyper_name);

> -            g_free(pmevtyper_el0_name);


TIL git-diff --color-moved

Maybe move PERFMON block first, then extract define_pmu_regs()?

In any case,
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>


> -        }

>           ARMCPRegInfo clidr = {

>               .name = "CLIDR", .state = ARM_CP_STATE_BOTH,

>               .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,

> @@ -6315,24 +6335,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)

>           define_one_arm_cp_reg(cpu, &clidr);

>           define_arm_cp_regs(cpu, v7_cp_reginfo);

>           define_debug_regs(cpu);

> +        define_pmu_regs(cpu);

>       } else {

>           define_arm_cp_regs(cpu, not_v7_cp_reginfo);

>       }

> -    if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&

> -            FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {

> -        ARMCPRegInfo v81_pmu_regs[] = {

> -            { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,

> -              .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,

> -              .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,

> -              .resetvalue = extract64(cpu->pmceid0, 32, 32) },

> -            { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,

> -              .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,

> -              .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,

> -              .resetvalue = extract64(cpu->pmceid1, 32, 32) },

> -            REGINFO_SENTINEL

> -        };

> -        define_arm_cp_regs(cpu, v81_pmu_regs);

> -    }

>       if (arm_feature(env, ARM_FEATURE_V8)) {

>           /* AArch64 ID registers, which all have impdef reset values.

>            * Note that within the ID register ranges the unused slots

>
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index bf083c369fc..0011a22f42d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5822,6 +5822,87 @@  static void define_debug_regs(ARMCPU *cpu)
     }
 }
 
+static void define_pmu_regs(ARMCPU *cpu)
+{
+    /*
+     * v7 performance monitor control register: same implementor
+     * field as main ID register, and we implement four counters in
+     * addition to the cycle count register.
+     */
+    unsigned int i, pmcrn = 4;
+    ARMCPRegInfo pmcr = {
+        .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
+        .access = PL0_RW,
+        .type = ARM_CP_IO | ARM_CP_ALIAS,
+        .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
+        .accessfn = pmreg_access, .writefn = pmcr_write,
+        .raw_writefn = raw_write,
+    };
+    ARMCPRegInfo pmcr64 = {
+        .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
+        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
+        .access = PL0_RW, .accessfn = pmreg_access,
+        .type = ARM_CP_IO,
+        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
+        .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
+        .writefn = pmcr_write, .raw_writefn = raw_write,
+    };
+    define_one_arm_cp_reg(cpu, &pmcr);
+    define_one_arm_cp_reg(cpu, &pmcr64);
+    for (i = 0; i < pmcrn; i++) {
+        char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
+        char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);
+        char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
+        char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
+        ARMCPRegInfo pmev_regs[] = {
+            { .name = pmevcntr_name, .cp = 15, .crn = 14,
+              .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
+              .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
+              .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
+              .accessfn = pmreg_access },
+            { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
+              .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
+              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
+              .type = ARM_CP_IO,
+              .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
+              .raw_readfn = pmevcntr_rawread,
+              .raw_writefn = pmevcntr_rawwrite },
+            { .name = pmevtyper_name, .cp = 15, .crn = 14,
+              .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
+              .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
+              .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
+              .accessfn = pmreg_access },
+            { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
+              .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
+              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
+              .type = ARM_CP_IO,
+              .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
+              .raw_writefn = pmevtyper_rawwrite },
+            REGINFO_SENTINEL
+        };
+        define_arm_cp_regs(cpu, pmev_regs);
+        g_free(pmevcntr_name);
+        g_free(pmevcntr_el0_name);
+        g_free(pmevtyper_name);
+        g_free(pmevtyper_el0_name);
+    }
+    if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
+            FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {
+        ARMCPRegInfo v81_pmu_regs[] = {
+            { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
+              .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
+              .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .resetvalue = extract64(cpu->pmceid0, 32, 32) },
+            { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
+              .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
+              .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .resetvalue = extract64(cpu->pmceid1, 32, 32) },
+            REGINFO_SENTINEL
+        };
+        define_arm_cp_regs(cpu, v81_pmu_regs);
+    }
+}
+
 /* We don't know until after realize whether there's a GICv3
  * attached, and that is what registers the gicv3 sysregs.
  * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
@@ -6244,67 +6325,6 @@  void register_cp_regs_for_features(ARMCPU *cpu)
         define_arm_cp_regs(cpu, pmovsset_cp_reginfo);
     }
     if (arm_feature(env, ARM_FEATURE_V7)) {
-        /* v7 performance monitor control register: same implementor
-         * field as main ID register, and we implement four counters in
-         * addition to the cycle count register.
-         */
-        unsigned int i, pmcrn = 4;
-        ARMCPRegInfo pmcr = {
-            .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
-            .access = PL0_RW,
-            .type = ARM_CP_IO | ARM_CP_ALIAS,
-            .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
-            .accessfn = pmreg_access, .writefn = pmcr_write,
-            .raw_writefn = raw_write,
-        };
-        ARMCPRegInfo pmcr64 = {
-            .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
-            .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
-            .access = PL0_RW, .accessfn = pmreg_access,
-            .type = ARM_CP_IO,
-            .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
-            .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
-            .writefn = pmcr_write, .raw_writefn = raw_write,
-        };
-        define_one_arm_cp_reg(cpu, &pmcr);
-        define_one_arm_cp_reg(cpu, &pmcr64);
-        for (i = 0; i < pmcrn; i++) {
-            char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
-            char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);
-            char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
-            char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
-            ARMCPRegInfo pmev_regs[] = {
-                { .name = pmevcntr_name, .cp = 15, .crn = 14,
-                  .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
-                  .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
-                  .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
-                  .accessfn = pmreg_access },
-                { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
-                  .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
-                  .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
-                  .type = ARM_CP_IO,
-                  .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
-                  .raw_readfn = pmevcntr_rawread,
-                  .raw_writefn = pmevcntr_rawwrite },
-                { .name = pmevtyper_name, .cp = 15, .crn = 14,
-                  .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
-                  .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
-                  .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
-                  .accessfn = pmreg_access },
-                { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
-                  .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
-                  .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
-                  .type = ARM_CP_IO,
-                  .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
-                  .raw_writefn = pmevtyper_rawwrite },
-                REGINFO_SENTINEL
-            };
-            define_arm_cp_regs(cpu, pmev_regs);
-            g_free(pmevcntr_name);
-            g_free(pmevcntr_el0_name);
-            g_free(pmevtyper_name);
-            g_free(pmevtyper_el0_name);
-        }
         ARMCPRegInfo clidr = {
             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
@@ -6315,24 +6335,10 @@  void register_cp_regs_for_features(ARMCPU *cpu)
         define_one_arm_cp_reg(cpu, &clidr);
         define_arm_cp_regs(cpu, v7_cp_reginfo);
         define_debug_regs(cpu);
+        define_pmu_regs(cpu);
     } else {
         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
     }
-    if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
-            FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {
-        ARMCPRegInfo v81_pmu_regs[] = {
-            { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
-              .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
-              .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
-              .resetvalue = extract64(cpu->pmceid0, 32, 32) },
-            { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
-              .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
-              .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
-              .resetvalue = extract64(cpu->pmceid1, 32, 32) },
-            REGINFO_SENTINEL
-        };
-        define_arm_cp_regs(cpu, v81_pmu_regs);
-    }
     if (arm_feature(env, ARM_FEATURE_V8)) {
         /* AArch64 ID registers, which all have impdef reset values.
          * Note that within the ID register ranges the unused slots