[v2,16/21] target/arm: Correct definition of PMCRDP

Message ID	20200214175116.9164-17-peter.maydell@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Peter Maydell <peter.maydell@linaro.org> To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 16/21] target/arm: Correct definition of PMCRDP Date: Fri, 14 Feb 2020 17:51:11 +0000 Message-Id: <20200214175116.9164-17-peter.maydell@linaro.org> In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: list Cc: Eric Auger <eric.auger@redhat.com>, Aaron Lindsay <aaron@os.amperecomputing.com>, Richard Henderson <richard.henderson@linaro.org>, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@redhat.com> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2 \| expand [v2,00/21] arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2 [v2,01/21] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers [v2,02/21] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan [v2,03/21] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions [v2,04/21] target/arm: Define and use any_predinv isar_feature test [v2,05/21] target/arm: Factor out PMU register definitions [v2,06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 [v2,07/21] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field [v2,08/21] target/arm: Define an aa32_pmu_8_1 isar feature test function [v2,09/21] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks [v2,10/21] target/arm: Stop assuming DBGDIDR always exists [v2,11/21] target/arm: Move DBGDIDR into ARMISARegisters [v2,12/21] target/arm: Read debug-related ID registers from KVM [v2,13/21] target/arm: Implement ARMv8.1-PMU extension [v2,14/21] target/arm: Implement ARMv8.4-PMU extension [v2,15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max' [v2,16/21] target/arm: Correct definition of PMCRDP [v2,17/21] target/arm: Correct handling of PMCR_EL0.LC bit [v2,18/21] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks [v2,19/21] target/arm: Use isar_feature function for testing AA32HPD feature [v2,20/21] target/arm: Use FIELD_EX32 for testing 32-bit fields [v2,21/21] target/arm: Correctly implement ACTLR2, HACTLR2

Message ID

20200214175116.9164-17-peter.maydell@linaro.org

State

Superseded

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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
	qemu-devel@nongnu.org
Subject: [PATCH v2 16/21] target/arm: Correct definition of PMCRDP
Date: Fri, 14 Feb 2020 17:51:11 +0000
Message-Id: <20200214175116.9164-17-peter.maydell@linaro.org>
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	<richard.henderson@linaro.org>, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?=
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Series

arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2 | expand

Commit Message

Peter Maydell Feb. 14, 2020, 5:51 p.m. UTC

The PMCR_EL0.DP bit is bit 5, which is 0x20, not 0x10.  0x10 is 'X'.
Correct our #define of PMCRDP and add the missing PMCRX.

We do have the correct behaviour for handling the DP bit being
set, so this fixes a guest-visible bug.

Fixes: 033614c47de
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/helper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

-- 
2.20.1

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2feded1518c..2ebfa6c6545 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1017,7 +1017,8 @@  static const ARMCPRegInfo v6_cp_reginfo[] = {
 #define PMCRN_MASK  0xf800
 #define PMCRN_SHIFT 11
 #define PMCRLC  0x40
-#define PMCRDP  0x10
+#define PMCRDP  0x20
+#define PMCRX   0x10
 #define PMCRD   0x8
 #define PMCRC   0x4
 #define PMCRP   0x2

[v2,16/21] target/arm: Correct definition of PMCRDP

Commit Message

Patch