[01/19] target/arm: Fix field extract from MVFR[0-2]

Message ID 20200214181547.21408-2-richard.henderson@linaro.org
State New
Headers show
Series
  • target/arm: vfp feature and decodetree cleanup
Related show

Commit Message

Richard Henderson Feb. 14, 2020, 6:15 p.m.
These registers are 32-bits wide.  Cut and paste used FIELD_EX64
instead of the more proper FIELD_EX32.  In practice all this did
was use an unnecessary 64-bit operation, producing correct results.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/cpu.h | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

-- 
2.20.1

Comments

Philippe Mathieu-Daudé Feb. 14, 2020, 6:29 p.m. | #1
On 2/14/20 7:15 PM, Richard Henderson wrote:
> These registers are 32-bits wide.  Cut and paste used FIELD_EX64

> instead of the more proper FIELD_EX32.  In practice all this did

> was use an unnecessary 64-bit operation, producing correct results.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>   target/arm/cpu.h | 18 +++++++++---------

>   1 file changed, 9 insertions(+), 9 deletions(-)

> 

> diff --git a/target/arm/cpu.h b/target/arm/cpu.h

> index e943ffe8a9..28cb2be6fc 100644

> --- a/target/arm/cpu.h

> +++ b/target/arm/cpu.h

> @@ -3415,18 +3415,18 @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)

>   static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id)

>   {

>       /* Return true if D16-D31 are implemented */

> -    return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >= 2;

> +    return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;

>   }

>   

>   static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)

>   {

> -    return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0;

> +    return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;

>   }

>   

>   static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)

>   {

>       /* Return true if CPU supports double precision floating point */

> -    return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0;

> +    return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;

>   }

>   

>   /*

> @@ -3436,32 +3436,32 @@ static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)

>    */

>   static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)

>   {

> -    return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;

> +    return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;

>   }

>   

>   static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)

>   {

> -    return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;

> +    return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;

>   }

>   

>   static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)

>   {

> -    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1;

> +    return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;

>   }

>   

>   static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)

>   {

> -    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2;

> +    return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;

>   }

>   

>   static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)

>   {

> -    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3;

> +    return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;

>   }

>   

>   static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)

>   {

> -    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;

> +    return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;

>   }

>   

>   static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)

> 


Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Peter Maydell Feb. 14, 2020, 6:35 p.m. | #2
On Fri, 14 Feb 2020 at 18:15, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> These registers are 32-bits wide.  Cut and paste used FIELD_EX64

> instead of the more proper FIELD_EX32.  In practice all this did

> was use an unnecessary 64-bit operation, producing correct results.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


This is a duplicate with:

https://patchew.org/QEMU/20200214175116.9164-1-peter.maydell@linaro.org/20200214175116.9164-21-peter.maydell@linaro.org/

which I got out the door very slightly before your series
hit my mailbox :-)

-- PMM

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e943ffe8a9..28cb2be6fc 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3415,18 +3415,18 @@  static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
 static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id)
 {
     /* Return true if D16-D31 are implemented */
-    return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >= 2;
+    return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
 }
 
 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
 {
-    return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0;
+    return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
 }
 
 static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
 {
     /* Return true if CPU supports double precision floating point */
-    return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0;
+    return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
 }
 
 /*
@@ -3436,32 +3436,32 @@  static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
  */
 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
 {
-    return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;
+    return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
 }
 
 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
 {
-    return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
+    return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
 }
 
 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
 {
-    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1;
+    return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
 }
 
 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
 {
-    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2;
+    return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
 }
 
 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
 {
-    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3;
+    return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
 }
 
 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
 {
-    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
+    return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
 }
 
 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)