diff mbox series

[3/4] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN

Message ID 20200214194643.23317-4-richard.henderson@linaro.org
State Accepted
Commit 33649de62e40df0060a1c514574e4ef25c4e52e1
Headers show
Series target/arm: fix some simd writes vs sve | expand

Commit Message

Richard Henderson Feb. 14, 2020, 7:46 p.m. UTC 
Writes to AdvSIMD registers flush the bits above 128.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/translate-a64.c | 1 +
 1 file changed, 1 insertion(+)

-- 
2.20.1
diff mbox series

Patch

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 096a854aed..b83d09dbcd 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7054,6 +7054,7 @@  static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_resl);
     write_vec_element(s, tcg_resh, rd, 1, MO_64);
     tcg_temp_free_i64(tcg_resh);
+    clear_vec_high(s, true, rd);
 }
 
 /*