[v3,6/7] target/arm: Honor the HCR_EL2.TPU bit

Message ID	20200218190958.745-7-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH v3 6/7] target/arm: Honor the HCR_EL2.TPU bit Date: Tue, 18 Feb 2020 11:09:57 -0800 Message-Id: <20200218190958.745-7-richard.henderson@linaro.org> In-Reply-To: <20200218190958.745-1-richard.henderson@linaro.org> References: <20200218190958.745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Honor more HCR_EL2 traps \| expand [v3,0/7] target/arm: Honor more HCR_EL2 traps [v3,1/7] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn [v3,2/7] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits [v3,3/7] target/arm: Honor the HCR_EL2.TSW bit [v3,4/7] target/arm: Honor the HCR_EL2.TACR bit [v3,5/7] target/arm: Honor the HCR_EL2.TPCP bit [v3,6/7] target/arm: Honor the HCR_EL2.TPU bit [v3,7/7] target/arm: Honor the HCR_EL2.TTLB bit

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20200218190958.745-7-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v3 6/7] target/arm: Honor the HCR_EL2.TPU bit
Date: Tue, 18 Feb 2020 11:09:57 -0800
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Series

target/arm: Honor more HCR_EL2 traps | expand

Commit Message

Richard Henderson Feb. 18, 2020, 7:09 p.m. UTC

This bit traps EL1 access to cache maintenance insns that operate
to the point of unification.  There are no longer any references to
plain aa64_cacheop_access, so remove it.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/helper.c | 53 +++++++++++++++++++++++++++------------------
 1 file changed, 32 insertions(+), 21 deletions(-)

-- 
2.20.1

Comments

Peter Maydell Feb. 25, 2020, 11:56 a.m. UTC | #1

On Tue, 18 Feb 2020 at 19:10, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> This bit traps EL1 access to cache maintenance insns that operate

> to the point of unification.  There are no longer any references to

> plain aa64_cacheop_access, so remove it.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/helper.c | 53 +++++++++++++++++++++++++++------------------

>  1 file changed, 32 insertions(+), 21 deletions(-)

>

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index ed34d4200f..21ee9cf7de 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -4301,19 +4301,6 @@ static const ARMCPRegInfo uao_reginfo = {

>      .readfn = aa64_uao_read, .writefn = aa64_uao_write

>  };

>

> -static CPAccessResult aa64_cacheop_access(CPUARMState *env,

> -                                          const ARMCPRegInfo *ri,

> -                                          bool isread)

> -{

> -    /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless

> -     * SCTLR_EL1.UCI is set.

> -     */

> -    if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) {

> -        return CP_ACCESS_TRAP;

> -    }

> -    return CP_ACCESS_OK;

> -}

> -

>  static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,

>                                                const ARMCPRegInfo *ri,

>                                                bool isread)

> @@ -4336,6 +4323,28 @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,

>      return CP_ACCESS_OK;

>  }

>

> +static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,

> +                                              const ARMCPRegInfo *ri,

> +                                              bool isread)

> +{

> +    /* Cache invalidate/clean to Point of Unification... */

> +    switch (arm_current_el(env)) {

> +    case 0:

> +        /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set.  */

> +        if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {

> +            return CP_ACCESS_TRAP;

> +        }

> +        break;


Again, we want to fall through here rather than breaking.

> +    case 1:

> +        /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set.  */

> +        if (arm_hcr_el2_eff(env) & HCR_TPU) {

> +            return CP_ACCESS_TRAP_EL2;

> +        }

> +        break;

> +    }

> +    return CP_ACCESS_OK;

> +}


thanks
-- PMM

diff --git a/target/arm/helper.c b/target/arm/helper.c
index ed34d4200f..21ee9cf7de 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4301,19 +4301,6 @@  static const ARMCPRegInfo uao_reginfo = {
     .readfn = aa64_uao_read, .writefn = aa64_uao_write
 };
 
-static CPAccessResult aa64_cacheop_access(CPUARMState *env,
-                                          const ARMCPRegInfo *ri,
-                                          bool isread)
-{
-    /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
-     * SCTLR_EL1.UCI is set.
-     */
-    if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) {
-        return CP_ACCESS_TRAP;
-    }
-    return CP_ACCESS_OK;
-}
-
 static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
                                               const ARMCPRegInfo *ri,
                                               bool isread)
@@ -4336,6 +4323,28 @@  static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
     return CP_ACCESS_OK;
 }
 
+static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
+                                              const ARMCPRegInfo *ri,
+                                              bool isread)
+{
+    /* Cache invalidate/clean to Point of Unification... */
+    switch (arm_current_el(env)) {
+    case 0:
+        /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set.  */
+        if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
+            return CP_ACCESS_TRAP;
+        }
+        break;
+    case 1:
+        /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set.  */
+        if (arm_hcr_el2_eff(env) & HCR_TPU) {
+            return CP_ACCESS_TRAP_EL2;
+        }
+        break;
+    }
+    return CP_ACCESS_OK;
+}
+
 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
  * Page D4-1736 (DDI0487A.b)
  */
@@ -4733,14 +4742,16 @@  static const ARMCPRegInfo v8_cp_reginfo[] = {
     /* Cache ops: all NOPs since we don't emulate caches */
     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
-      .access = PL1_W, .type = ARM_CP_NOP },
+      .access = PL1_W, .type = ARM_CP_NOP,
+      .accessfn = aa64_cacheop_pou_access },
     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
-      .access = PL1_W, .type = ARM_CP_NOP },
+      .access = PL1_W, .type = ARM_CP_NOP,
+      .accessfn = aa64_cacheop_pou_access },
     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
-      .accessfn = aa64_cacheop_access },
+      .accessfn = aa64_cacheop_pou_access },
     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
       .access = PL1_W, .accessfn = aa64_cacheop_poc_access,
@@ -4758,7 +4769,7 @@  static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
-      .accessfn = aa64_cacheop_access },
+      .accessfn = aa64_cacheop_pou_access },
     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
@@ -4932,13 +4943,13 @@  static const ARMCPRegInfo v8_cp_reginfo[] = {
       .writefn = tlbiipas2_is_write },
     /* 32 bit cache operations */
     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
-      .type = ARM_CP_NOP, .access = PL1_W },
+      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
       .type = ARM_CP_NOP, .access = PL1_W },
     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
-      .type = ARM_CP_NOP, .access = PL1_W },
+      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
-      .type = ARM_CP_NOP, .access = PL1_W },
+      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
       .type = ARM_CP_NOP, .access = PL1_W },
     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
@@ -4952,7 +4963,7 @@  static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
-      .type = ARM_CP_NOP, .access = PL1_W },
+      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,

[v3,6/7] target/arm: Honor the HCR_EL2.TPU bit

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