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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 05/17] target/arm: Improve ID_AA64PFR0 FP/SIMD validation Date: Mon, 24 Feb 2020 14:22:20 -0800 Message-Id: <20200224222232.13807-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When sanity checking id_aa64pfr0, use the raw FP and SIMD fields, because the values must match. Delay the test until we've finished modifying the id_aa64pfr0 register. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5be4c25809..f10f34b655 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1427,17 +1427,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) return; } - if (arm_feature(env, ARM_FEATURE_AARCH64) && - cpu->has_vfp != cpu->has_neon) { - /* - * This is an architectural requirement for AArch64; AArch32 is - * more flexible and permits VFP-no-Neon and Neon-no-VFP. - */ - error_setg(errp, - "AArch64 CPUs must have both VFP and Neon or neither"); - return; - } - if (!cpu->has_vfp) { uint64_t t; uint32_t u; @@ -1537,6 +1526,18 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->isar.mvfr0 = u; } + if (arm_feature(env, ARM_FEATURE_AARCH64) && + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, FP) != + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, ADVSIMD)) { + /* + * This is an architectural requirement for AArch64. Not only + * both vfp and advsimd or neither, but further both must + * support fp16 or neither. + */ + error_setg(errp, "AArch64 CPUs must match VFP and NEON"); + return; + } + if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { uint32_t u;