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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id d69sm19069704pfd.72.2020.02.25.10.08.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2020 10:08:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 1/7] target/arm: Improve masking of HCR RES0 bits Date: Tue, 25 Feb 2020 10:08:25 -0800 Message-Id: <20200225180831.26078-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200225180831.26078-1-richard.henderson@linaro.org> References: <20200225180831.26078-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Don't merely start with v8.0, handle v7VE as well. Notice writes from aarch32 mode, and the bits that ought not be settable from there. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 79db169e04..d65160fdb3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5089,8 +5089,13 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = env_archcpu(env); - /* Begin with bits defined in base ARMv8.0. */ - uint64_t valid_mask = MAKE_64BIT_MASK(0, 34); + uint64_t valid_mask; + + if (arm_feature(env, ARM_FEATURE_V8)) { + valid_mask = MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ + } else { + valid_mask = MAKE_64BIT_MASK(0, 28); /* ARMv7VE */ + } if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &= ~HCR_HCD; @@ -5114,6 +5119,14 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) valid_mask |= HCR_API | HCR_APK; } + if (ri->state == ARM_CP_STATE_AA32) { + /* + * Writes from aarch32 mode have more RES0 bits. + * This includes TDZ, RW, E2H, and more. + */ + valid_mask &= ~0xff80ff8c90000000ull; + } + /* Clear RES0 bits. */ value &= valid_mask;