[v7,00/42] target/arm: Implement ARMv8.5-MemTag, system mode

Message ID 20200603011317.473934-1-richard.henderson@linaro.org
State New
Headers show

Commit Message

Richard Henderson June 3, 2020, 1:12 a.m.
Version 6 was back in March:
https://lists.nongnu.org/archive/html/qemu-devel/2020-03/msg03790.html

Version 7 is a rebase on master, which now contains all prereqs.
In addition, two bugs fixed, pointed out by users of the branch.

I've done light testing against

https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=devel/mte-v4

I still have not implemented the arm,armv8.5-memtag OF property
expected by that branch, so I have been disabling it.


r~




Richard Henderson (42):
  target/arm: Add isar tests for mte
  target/arm: Improve masking of SCR RES0 bits
  target/arm: Add support for MTE to SCTLR_ELx
  target/arm: Add support for MTE to HCR_EL2 and SCR_EL3
  target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT
  target/arm: Add DISAS_UPDATE_NOCHAIN
  target/arm: Add MTE system registers
  target/arm: Add MTE bits to tb_flags
  target/arm: Implement the IRG instruction
  target/arm: Implement the ADDG, SUBG instructions
  target/arm: Implement the GMI instruction
  target/arm: Implement the SUBP instruction
  target/arm: Define arm_cpu_do_unaligned_access for user-only
  target/arm: Add helper_probe_access
  target/arm: Implement LDG, STG, ST2G instructions
  target/arm: Implement the STGP instruction
  target/arm: Restrict the values of DCZID.BS under TCG
  target/arm: Simplify DC_ZVA
  target/arm: Implement the LDGM, STGM, STZGM instructions
  target/arm: Implement the access tag cache flushes
  target/arm: Move regime_el to internals.h
  target/arm: Move regime_tcr to internals.h
  target/arm: Add gen_mte_check1
  target/arm: Add gen_mte_checkN
  target/arm: Implement helper_mte_check1
  target/arm: Implement helper_mte_checkN
  target/arm: Add helper_mte_check_zva
  target/arm: Use mte_checkN for sve unpredicated loads
  target/arm: Use mte_checkN for sve unpredicated stores
  target/arm: Use mte_check1 for sve LD1R
  target/arm: Add mte helpers for sve scalar + int loads
  target/arm: Add mte helpers for sve scalar + int stores
  target/arm: Add mte helpers for sve scalar + int ff/nf loads
  target/arm: Handle TBI for sve scalar + int memory ops
  target/arm: Add mte helpers for sve scatter/gather memory ops
  target/arm: Complete TBI clearing for user-only for SVE
  target/arm: Implement data cache set allocation tags
  target/arm: Set PSTATE.TCO on exception entry
  target/arm: Enable MTE
  target/arm: Cache the Tagged bit for a page in MemTxAttrs
  target/arm: Create tagged ram when MTE is enabled
  target/arm: Add allocation tag storage for system mode

 target/arm/cpu.h               |   36 +-
 target/arm/helper-a64.h        |   16 +
 target/arm/helper-sve.h        |  491 +++++++++++
 target/arm/helper.h            |    2 +
 target/arm/internals.h         |  148 ++++
 target/arm/translate-a64.h     |    5 +
 target/arm/translate.h         |   23 +-
 hw/arm/virt.c                  |   52 ++
 linux-user/aarch64/cpu_loop.c  |    7 +
 linux-user/arm/cpu_loop.c      |    7 +
 target/arm/cpu.c               |   77 +-
 target/arm/cpu64.c             |    1 +
 target/arm/helper-a64.c        |   94 +--
 target/arm/helper.c            |  350 ++++++--
 target/arm/mte_helper.c        |  897 ++++++++++++++++++++
 target/arm/op_helper.c         |   16 +
 target/arm/sve_helper.c        |  746 ++++++++++++++---
 target/arm/tlb_helper.c        |   41 +-
 target/arm/translate-a64.c     |  607 ++++++++++++--
 target/arm/translate-sve.c     | 1421 ++++++++++++++++++++------------
 target/arm/translate-vfp.inc.c |    2 +-
 target/arm/translate.c         |   16 +-
 target/arm/Makefile.objs       |    1 +
 23 files changed, 4206 insertions(+), 850 deletions(-)
 create mode 100644 target/arm/mte_helper.c

-- 
2.25.1

Comments

no-reply@patchew.org June 3, 2020, 2:15 a.m. | #1
Patchew URL: https://patchew.org/QEMU/20200603011317.473934-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20200603011317.473934-1-richard.henderson@linaro.org
Subject: [PATCH v7 00/42] target/arm: Implement ARMv8.5-MemTag, system mode
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20200603011317.473934-1-richard.henderson@linaro.org -> patchew/20200603011317.473934-1-richard.henderson@linaro.org
 * [new tag]         patchew/20200603013603.2400199-1-eblake@redhat.com -> patchew/20200603013603.2400199-1-eblake@redhat.com
 * [new tag]         patchew/20200603020208.2089-1-fangying1@huawei.com -> patchew/20200603020208.2089-1-fangying1@huawei.com
Switched to a new branch 'test'
62fe299 target/arm: Add allocation tag storage for system mode
7e853b6 target/arm: Create tagged ram when MTE is enabled
0f7ab37 target/arm: Cache the Tagged bit for a page in MemTxAttrs
bce00b5 target/arm: Enable MTE
39c912c target/arm: Set PSTATE.TCO on exception entry
7e09fd1 target/arm: Implement data cache set allocation tags
226fcf6 target/arm: Complete TBI clearing for user-only for SVE
010fffd target/arm: Add mte helpers for sve scatter/gather memory ops
216f125 target/arm: Handle TBI for sve scalar + int memory ops
a7312b3 target/arm: Add mte helpers for sve scalar + int ff/nf loads
a11212f target/arm: Add mte helpers for sve scalar + int stores
a41c42e target/arm: Add mte helpers for sve scalar + int loads
5f0a8f9 target/arm: Use mte_check1 for sve LD1R
0b652b7 target/arm: Use mte_checkN for sve unpredicated stores
d24b05b target/arm: Use mte_checkN for sve unpredicated loads
e9ff3e1 target/arm: Add helper_mte_check_zva
396d638 target/arm: Implement helper_mte_checkN
137dce2 target/arm: Implement helper_mte_check1
16927bf target/arm: Add gen_mte_checkN
84f03dd target/arm: Add gen_mte_check1
cb2f1f3 target/arm: Move regime_tcr to internals.h
1983d92 target/arm: Move regime_el to internals.h
1faf997 target/arm: Implement the access tag cache flushes
0c1ab5a target/arm: Implement the LDGM, STGM, STZGM instructions
f748125 target/arm: Simplify DC_ZVA
d5f7750 target/arm: Restrict the values of DCZID.BS under TCG
8988c38 target/arm: Implement the STGP instruction
6571a20 target/arm: Implement LDG, STG, ST2G instructions
b68fe26 target/arm: Add helper_probe_access
5443ae8 target/arm: Define arm_cpu_do_unaligned_access for user-only
bada4a1 target/arm: Implement the SUBP instruction
8e841fa target/arm: Implement the GMI instruction
8d1f1bd target/arm: Implement the ADDG, SUBG instructions
ecd3b81 target/arm: Implement the IRG instruction
afca8f1 target/arm: Add MTE bits to tb_flags
0f5b5bc target/arm: Add MTE system registers
a67e1280 target/arm: Add DISAS_UPDATE_NOCHAIN
b7d57c4 target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT
e60cd5e target/arm: Add support for MTE to HCR_EL2 and SCR_EL3
ea0858f target/arm: Add support for MTE to SCTLR_ELx
1eb3cd5 target/arm: Improve masking of SCR RES0 bits
5199961 target/arm: Add isar tests for mte

=== OUTPUT BEGIN ===
1/42 Checking commit 5199961fd247 (target/arm: Add isar tests for mte)
2/42 Checking commit 1eb3cd586775 (target/arm: Improve masking of SCR RES0 bits)
3/42 Checking commit ea0858fbc855 (target/arm: Add support for MTE to SCTLR_ELx)
4/42 Checking commit e60cd5e319ed (target/arm: Add support for MTE to HCR_EL2 and SCR_EL3)
5/42 Checking commit b7d57c4df890 (target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT)
6/42 Checking commit a67e12801405 (target/arm: Add DISAS_UPDATE_NOCHAIN)
7/42 Checking commit 0f5b5bc435d8 (target/arm: Add MTE system registers)
8/42 Checking commit afca8f129b24 (target/arm: Add MTE bits to tb_flags)
ERROR: trailing whitespace
#97: FILE: target/arm/helper.c:12716:
+        flags = FIELD_DP32(flags, TBFLAG_A64, TCMA, $

total: 1 errors, 0 warnings, 133 lines checked

Patch 8/42 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

9/42 Checking commit ecd3b81afa58 (target/arm: Implement the IRG instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#44: 
new file mode 100644

total: 0 errors, 1 warnings, 120 lines checked

Patch 9/42 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/42 Checking commit 8d1f1bd061b6 (target/arm: Implement the ADDG, SUBG instructions)
11/42 Checking commit 8e841fa9738c (target/arm: Implement the GMI instruction)
12/42 Checking commit bada4a1dcba2 (target/arm: Implement the SUBP instruction)
13/42 Checking commit 5443ae828687 (target/arm: Define arm_cpu_do_unaligned_access for user-only)
14/42 Checking commit b68fe26dc8cc (target/arm: Add helper_probe_access)
15/42 Checking commit 6571a2093448 (target/arm: Implement LDG, STG, ST2G instructions)
16/42 Checking commit 8988c38981e8 (target/arm: Implement the STGP instruction)
ERROR: suspect code indent for conditional statements (8, 13)
#63: FILE: target/arm/translate-a64.c:2782:
+        if (!s->ata) {
+             /*

total: 1 errors, 0 warnings, 60 lines checked

Patch 16/42 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

17/42 Checking commit d5f77508bc46 (target/arm: Restrict the values of DCZID.BS under TCG)
18/42 Checking commit f748125bcd28 (target/arm: Simplify DC_ZVA)
19/42 Checking commit 0c1ab5a0b13b (target/arm: Implement the LDGM, STGM, STZGM instructions)
20/42 Checking commit 1faf997ec0ad (target/arm: Implement the access tag cache flushes)
21/42 Checking commit 1983d925203c (target/arm: Move regime_el to internals.h)
22/42 Checking commit cb2f1f365808 (target/arm: Move regime_tcr to internals.h)
23/42 Checking commit 84f03dd79250 (target/arm: Add gen_mte_check1)
WARNING: line over 80 characters
#176: FILE: target/arm/translate-a64.c:2554:
+        clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn != 31, size);

WARNING: line over 80 characters
#194: FILE: target/arm/translate-a64.c:2590:
+        clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn != 31, size);

total: 0 errors, 2 warnings, 242 lines checked

Patch 23/42 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
24/42 Checking commit 16927bf546ee (target/arm: Add gen_mte_checkN)
ERROR: trailing whitespace
#51: FILE: target/arm/translate-a64.c:288:
+ * For MTE, check multiple logical sequential accesses.  $

total: 1 errors, 0 warnings, 157 lines checked

Patch 24/42 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

25/42 Checking commit 137dce23357e (target/arm: Implement helper_mte_check1)
WARNING: line over 80 characters
#21: FILE: target/arm/internals.h:1322:
+uint64_t mte_check1(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);

total: 0 errors, 1 warnings, 194 lines checked

Patch 25/42 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/42 Checking commit 396d638c372e (target/arm: Implement helper_mte_checkN)
WARNING: line over 80 characters
#20: FILE: target/arm/internals.h:1323:
+uint64_t mte_checkN(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);

total: 0 errors, 1 warnings, 178 lines checked

Patch 26/42 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
27/42 Checking commit e9ff3e16cc15 (target/arm: Add helper_mte_check_zva)
28/42 Checking commit d24b05b1e447 (target/arm: Use mte_checkN for sve unpredicated loads)
29/42 Checking commit 0b652b7d7032 (target/arm: Use mte_checkN for sve unpredicated stores)
30/42 Checking commit 5f0a8f9e0498 (target/arm: Use mte_check1 for sve LD1R)
31/42 Checking commit a41c42e43d12 (target/arm: Add mte helpers for sve scalar + int loads)
32/42 Checking commit a11212facadb (target/arm: Add mte helpers for sve scalar + int stores)
33/42 Checking commit a7312b3bf65a (target/arm: Add mte helpers for sve scalar + int ff/nf loads)
34/42 Checking commit 216f1256e6d7 (target/arm: Handle TBI for sve scalar + int memory ops)
35/42 Checking commit 010fffd83232 (target/arm: Add mte helpers for sve scatter/gather memory ops)
36/42 Checking commit 226fcf6b1d07 (target/arm: Complete TBI clearing for user-only for SVE)
ERROR: code indent should never use tabs
#33: FILE: target/arm/sve_helper.c:3970:
+        (TYPEM)TLB(env, useronly_clean_ptr(addr), ra);^I                    \$

ERROR: spaces required around that '*' (ctx:VxV)
#42: FILE: target/arm/sve_helper.c:3978:
+        (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra);                            \
                ^

total: 2 errors, 0 warnings, 37 lines checked

Patch 36/42 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

37/42 Checking commit 7e09fd1a2bec (target/arm: Implement data cache set allocation tags)
38/42 Checking commit 39c912cf7764 (target/arm: Set PSTATE.TCO on exception entry)
39/42 Checking commit bce00b5ccceb (target/arm: Enable MTE)
40/42 Checking commit 0f7ab37fedd7 (target/arm: Cache the Tagged bit for a page in MemTxAttrs)
41/42 Checking commit 7e853b6dc32f (target/arm: Create tagged ram when MTE is enabled)
42/42 Checking commit 62fe2991b255 (target/arm: Add allocation tag storage for system mode)
WARNING: line over 80 characters
#82: FILE: target/arm/mte_helper.c:130:
+    /* If not normal memory, tag storage is not implemented, access unchecked. */

total: 0 errors, 1 warnings, 142 lines checked

Patch 42/42 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200603011317.473934-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
Richard Henderson June 3, 2020, 4:07 a.m. | #2
On 6/2/20 7:15 PM, no-reply@patchew.org wrote:
> This series seems to have some coding style problems.


Hmph, some of these are real.
I'll fix for v8, with other review.


r~
Peter Maydell June 19, 2020, 2:38 p.m. | #3
On Wed, 3 Jun 2020 at 02:13, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Version 6 was back in March:

> https://lists.nongnu.org/archive/html/qemu-devel/2020-03/msg03790.html

>

> Version 7 is a rebase on master, which now contains all prereqs.


I'm now done with my review pass on this version of the patchset.

thanks
-- PMM

Patch

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index b297a37c1b13..b5f18e63f8d1 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -155,6 +155,7 @@  s64 mte_ftr_filter
                return ID_AA64PFR1_MTE_NI;
        }
 
+#if 0
        /* check the DT "memory" nodes for MTE support */
        for_each_node_by_type(np, "memory") {
                memory_checked = true;
@@ -167,6 +168,7 @@  s64 mte_ftr_filter
                mte_capable = false;
                return ID_AA64PFR1_MTE_NI;
        }
+#endif
 
        return val;
 }