[v7,39/42] target/arm: Enable MTE

Message ID 20200603011317.473934-40-richard.henderson@linaro.org
State Superseded
Headers show
Series
  • [v7,01/42] target/arm: Add isar tests for mte
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Commit Message

Richard Henderson June 3, 2020, 1:13 a.m.
We now implement all of the components of MTE, without actually
supporting any tagged memory.  All MTE instructions will work,
trivially, so we can enable support.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
v6: Delay user-only cpu reset bits to the user-only patch set.
---
 target/arm/cpu64.c | 1 +
 1 file changed, 1 insertion(+)

-- 
2.25.1

Comments

Peter Maydell June 18, 2020, 4:39 p.m. | #1
On Wed, 3 Jun 2020 at 02:14, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> We now implement all of the components of MTE, without actually

> supporting any tagged memory.  All MTE instructions will work,

> trivially, so we can enable support.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

> v6: Delay user-only cpu reset bits to the user-only patch set.

> ---

>  target/arm/cpu64.c | 1 +

>  1 file changed, 1 insertion(+)

>

> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

> index cbc5c3868f..e4bce55c5f 100644

> --- a/target/arm/cpu64.c

> +++ b/target/arm/cpu64.c

> @@ -655,6 +655,7 @@ static void aarch64_max_initfn(Object *obj)

>

>          t = cpu->isar.id_aa64pfr1;

>          t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);

> +        t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);

>          cpu->isar.id_aa64pfr1 = t;


If we don't actually have tagged memory yet should we really
set the MTE field to 2 rather than 1 ?

thanks
-- PMM
Richard Henderson June 18, 2020, 5:35 p.m. | #2
On 6/18/20 9:39 AM, Peter Maydell wrote:
>>          t = cpu->isar.id_aa64pfr1;

>>          t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);

>> +        t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);

>>          cpu->isar.id_aa64pfr1 = t;

> 

> If we don't actually have tagged memory yet should we really

> set the MTE field to 2 rather than 1 ?


Well, we reduce that later in arm_cpu_realizefn.
But perhaps this patch should be sorted after patch 41.


r~

Patch

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index cbc5c3868f..e4bce55c5f 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -655,6 +655,7 @@  static void aarch64_max_initfn(Object *obj)
 
         t = cpu->isar.id_aa64pfr1;
         t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
+        t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
         cpu->isar.id_aa64pfr1 = t;
 
         t = cpu->isar.id_aa64mmfr1;