[v7,41/42] target/arm: Create tagged ram when MTE is enabled

Message ID 20200603011317.473934-42-richard.henderson@linaro.org
State New
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Series
  • [v7,01/42] target/arm: Add isar tests for mte
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Commit Message

Richard Henderson June 3, 2020, 1:13 a.m.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
v5: Assign cs->num_ases to the final value first.
    Downgrade to ID_AA64PFR1.MTE=1 if tag memory is not available.
v6: Add secure tag memory for EL3.
---
 target/arm/cpu.h |  6 ++++++
 hw/arm/virt.c    | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
 target/arm/cpu.c | 51 ++++++++++++++++++++++++++++++++++++++++++++---
 3 files changed, 106 insertions(+), 3 deletions(-)

-- 
2.25.1

Comments

Peter Maydell June 19, 2020, 2:37 p.m. | #1
On Wed, 3 Jun 2020 at 02:14, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

> v5: Assign cs->num_ases to the final value first.

>     Downgrade to ID_AA64PFR1.MTE=1 if tag memory is not available.

> v6: Add secure tag memory for EL3.

> ---



>  static void arm_cpu_finalizefn(Object *obj)

> @@ -1735,17 +1754,43 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

>      MachineState *ms = MACHINE(qdev_get_machine());

>      unsigned int smp_cpus = ms->smp.cpus;

>

> -    if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {

> +    /*

> +     * We must set cs->num_ases to the final value before

> +     * the first call to cpu_address_space_init.

> +     */

> +    if (cpu->tag_memory != NULL) {

> +        cs->num_ases = 4;

> +    } else if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {

>          cs->num_ases = 2;

> +    } else {

> +        cs->num_ases = 1;

> +    }


1: neither MTE nor TrustZone
2: TrustZone but not MTE
...but why is MTE always 4 even if no TrustZone? I would have
expected MTE-no-TZ to have 2 ASes...

> +    if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {

>          if (!cpu->secure_memory) {

>              cpu->secure_memory = cs->memory;

>          }

>          cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",

>                                 cpu->secure_memory);

> -    } else {

> -        cs->num_ases = 1;

>      }

> +

> +    if (cpu->tag_memory != NULL) {

> +        cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory",

> +                               cpu->tag_memory);

> +        if (cpu->has_el3) {

> +            cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",

> +                                   cpu->secure_tag_memory);

> +        }

> +    } else if (cpu_isar_feature(aa64_mte, cpu)) {

> +        /*

> +         * Since there is no tag memory, we can't meaningfully support MTE

> +         * to its fullest.  To avoid problems later, when we would come to

> +         * use the tag memory, downgrade support to insns only.

> +         */

> +        cpu->isar.id_aa64pfr1 =

> +            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);

> +    }

> +

>      cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);


...and indeed the code here only inits the ARMASIdx_NS and
ARMASIdx_TagNS spaces in that case. I guess we need to leave
ARMASIdx_S in the array but unused since we're effectively
indexing them by constant integer, but even so shouldn't
num_ases be 3 (0 and 2 used, 1 present but empty, 3 not needed) ?

thanks
-- PMM

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 17594226eb..deb270f25b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -792,6 +792,10 @@  struct ARMCPU {
     /* MemoryRegion to use for secure physical accesses */
     MemoryRegion *secure_memory;
 
+    /* MemoryRegion to use for allocation tag accesses */
+    MemoryRegion *tag_memory;
+    MemoryRegion *secure_tag_memory;
+
     /* For v8M, pointer to the IDAU interface provided by board/SoC */
     Object *idau;
 
@@ -2985,6 +2989,8 @@  typedef enum ARMMMUIdxBit {
 typedef enum ARMASIdx {
     ARMASIdx_NS = 0,
     ARMASIdx_S = 1,
+    ARMASIdx_TagNS = 2,
+    ARMASIdx_TagS = 3,
 } ARMASIdx;
 
 /* Return the Exception Level targeted by debug exceptions. */
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 37462a6f78..c74cc3d78d 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1412,6 +1412,16 @@  static void create_secure_ram(VirtMachineState *vms,
     g_free(nodename);
 }
 
+static void create_tag_ram(MemoryRegion *tag_sysmem,
+                           hwaddr base, hwaddr size,
+                           const char *name)
+{
+    MemoryRegion *tagram = g_new(MemoryRegion, 1);
+
+    memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
+    memory_region_add_subregion(tag_sysmem, base / 32, tagram);
+}
+
 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
 {
     const VirtMachineState *board = container_of(binfo, VirtMachineState,
@@ -1665,6 +1675,8 @@  static void machvirt_init(MachineState *machine)
     const CPUArchIdList *possible_cpus;
     MemoryRegion *sysmem = get_system_memory();
     MemoryRegion *secure_sysmem = NULL;
+    MemoryRegion *tag_sysmem = NULL;
+    MemoryRegion *secure_tag_sysmem = NULL;
     int n, virt_max_cpus;
     bool firmware_loaded;
     bool aarch64 = true;
@@ -1819,6 +1831,35 @@  static void machvirt_init(MachineState *machine)
                                      "secure-memory", &error_abort);
         }
 
+        /*
+         * The cpu adds the property if and only if MemTag is supported.
+         * If it is, we must allocate the ram to back that up.
+         */
+        if (object_property_find(cpuobj, "tag-memory", NULL)) {
+            if (!tag_sysmem) {
+                tag_sysmem = g_new(MemoryRegion, 1);
+                memory_region_init(tag_sysmem, OBJECT(machine),
+                                   "tag-memory", UINT64_MAX / 32);
+
+                if (vms->secure) {
+                    secure_tag_sysmem = g_new(MemoryRegion, 1);
+                    memory_region_init(secure_tag_sysmem, OBJECT(machine),
+                                       "secure-tag-memory", UINT64_MAX / 32);
+
+                    /* As with ram, secure-tag takes precedence over tag.  */
+                    memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
+                                                        tag_sysmem, -1);
+                }
+            }
+
+            object_property_set_link(cpuobj, OBJECT(tag_sysmem),
+                                     "tag-memory", &error_abort);
+            if (vms->secure) {
+                object_property_set_link(cpuobj, OBJECT(secure_tag_sysmem),
+                                         "secure-tag-memory", &error_abort);
+            }
+        }
+
         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
         object_unref(cpuobj);
     }
@@ -1861,6 +1902,17 @@  static void machvirt_init(MachineState *machine)
         create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
     }
 
+    if (tag_sysmem) {
+        create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
+                       machine->ram_size, "mach-virt.tag");
+        if (vms->secure) {
+            create_tag_ram(secure_tag_sysmem,
+                           vms->memmap[VIRT_SECURE_MEM].base,
+                           vms->memmap[VIRT_SECURE_MEM].size,
+                           "mach-virt.secure-tag");
+        }
+    }
+
     vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
 
     create_rtc(vms);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 8e6d4371cb..37b7cc2c9c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1245,6 +1245,25 @@  void arm_cpu_post_init(Object *obj)
     if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
         qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
     }
+
+#ifndef CONFIG_USER_ONLY
+    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) &&
+        cpu_isar_feature(aa64_mte, cpu)) {
+        object_property_add_link(obj, "tag-memory",
+                                 TYPE_MEMORY_REGION,
+                                 (Object **)&cpu->tag_memory,
+                                 qdev_prop_allow_set_link_before_realize,
+                                 OBJ_PROP_LINK_STRONG);
+
+        if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
+            object_property_add_link(obj, "secure-tag-memory",
+                                     TYPE_MEMORY_REGION,
+                                     (Object **)&cpu->secure_tag_memory,
+                                     qdev_prop_allow_set_link_before_realize,
+                                     OBJ_PROP_LINK_STRONG);
+        }
+    }
+#endif
 }
 
 static void arm_cpu_finalizefn(Object *obj)
@@ -1735,17 +1754,43 @@  static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     MachineState *ms = MACHINE(qdev_get_machine());
     unsigned int smp_cpus = ms->smp.cpus;
 
-    if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+    /*
+     * We must set cs->num_ases to the final value before
+     * the first call to cpu_address_space_init.
+     */
+    if (cpu->tag_memory != NULL) {
+        cs->num_ases = 4;
+    } else if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
         cs->num_ases = 2;
+    } else {
+        cs->num_ases = 1;
+    }
 
+    if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
         if (!cpu->secure_memory) {
             cpu->secure_memory = cs->memory;
         }
         cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
                                cpu->secure_memory);
-    } else {
-        cs->num_ases = 1;
     }
+
+    if (cpu->tag_memory != NULL) {
+        cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory",
+                               cpu->tag_memory);
+        if (cpu->has_el3) {
+            cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
+                                   cpu->secure_tag_memory);
+        }
+    } else if (cpu_isar_feature(aa64_mte, cpu)) {
+        /*
+         * Since there is no tag memory, we can't meaningfully support MTE
+         * to its fullest.  To avoid problems later, when we would come to
+         * use the tag memory, downgrade support to insns only.
+         */
+        cpu->isar.id_aa64pfr1 =
+            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
+    }
+
     cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
 
     /* No core_count specified, default to smp_cpus. */